Abstract: A Hall element is formed in one surface of a silicon die. A trench is etched away in the opposite die surface in a region adjacent the Hall element. An insulating silicon dioxide is grown on both surfaces and a layer of ferromagnetic metal is deposited on both surfaces to form a pair of pole pieces intimately integrated with the Hall element.

Abstract: A gate-array device has a plurality of basic cell lines in the central portion of a semiconductor chip and a plurality of I/O cells at its peripheral portion, the basic cell lines being composed of a plurality of basic cells in which at least one P-channel MOS FET and at least one N-channel MOS FET are disposed in a direction perpendicular to the basic cell lines. In each of the basic cell lines, a predetermined number of P-channel MOS FET's and the predetermined number of N-channel MOS FET's are alternatively disposed in a direction in parallel to the basic cell lines.

Abstract: In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Abstract: An integrated circuit devicer package includes a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers, and the I.C. chip. A dam structure prevents resin flow to ensure proper wire bonding and a wedge prevents electrical shorting. A recognition pattern enables precise wire bonding. A epoxy molding compound is interposed in cavities formed in a Kapton layer to preclude delamination.

Abstract: There is disclosed a light emitting device which includes a header and an angle stripe light emitting diode. The header has a longitudinal axis and a forward mounting surface. The forward mounting surface includes a leading edge portion which extends perpendicular to the longitudinal axis. The mounting surface further includes a trailing alignment edge portion which extends rearwardly from the leading edge portion at a predetermined compensating angle. The light emitting diode is affixed in electrical and heat transfer relation to the mounting surface of the header such that the emitting facet is aligned with the trailing alignment edge portion of the header. The trailing alignment edge portion compensates for the offset angle that light is emitted from a stripe light emitting diode.

Abstract: A quasi 1-dimensional electron gas transistor has been provided having a source electrode and a drain electrode. A plurality of electrodes are positioned between the source and drain electrodes in a manner which are parallel to the electron flow between the source and the drain electrodes. In one embodiment, the electrodes are interconnected by a gate electrode while in an alternate embodiment all the electrodes are connected to the source electrode and insulated from the gate electrode. This device provides a quantum wire for quasi 1-dimensional electron flow.

Abstract: The specification describes an epitaxial structure designed to reduce or eliminate the bowing of semiconductor wafers due to stresses caused by lattice mismatch between a heavily boron doped substrate and a lightly doped epitaxial layer. The lattice mismatch is reduced or eliminated by doping germanium into the substrate prior to epitaxial growth.

Abstract: An improved p-type semiconductor alloy film, an improved substantially intrinsic amorphous semiconductor alloy film, improved photovoltaic and photoresponsive devices incorporating such films and r.f. and microwave glow discharge methods for fabricating same. The improved semiconductor alloy films preferably include at least silicon deposited by the glow discharge of a compound containing at least silicon and a boron species that remains substantially monoatomic as it is incorporated into the silicon matrix. The p-type film is particularly stable, is characterized by a non-narrowed band gap, reduced bulk stress, improved morphology, growth and adhesion and reduced peeling and cracking. The substantially intrinsic film is characterized by substantially reduced Staebler-Wronski degradation. The method includes the novel step of introducing a boron species that does not form higher order boron hydrides or other boron polymers or oligomers in the glow discharge plasma.

Abstract: Disclosed is a superconducting Josephson junction which comprises a layer of niobium nitride on a substrate, an epitaxial layer of a pseudo-binary compound on the layer of niobium nitride, where the pseudo-binary compound has the composition about 3 atomic percent MgO--about 97 atomic percent CaO, to about 97 atomic percent MgO--about 3 atomic percent CaO, and an epitaxial layer of niobium nitride on the layer of pseudo-binary compound. Also disclosed is a method of making a Josephson junction by depositing a layer of niobium nitride onto a suitable substrate, depositing an expitaxial layer of a pseudo-binary compound onto the layer of niobium nitride, where the pseudo-binary compound has a composition of about 3 atomic percent MgO--about 97 atomic percent CaO, to about 97 atomic percent MgO--about 3 atomic percent CaO, and depositing an epitaxial layer of niobium nitride onto the layer said pseudo-binary compound.

Abstract: Special absorbers or getters are incorporated in hermetically sealed electronic circuits with organic components, for example, with parylene passivations, silver conductive adhesives, and sealing materials. The getter material, preferably BaAl.sub.4, is dispersed as an extremely fine-grained powder in a gas permeable, inert silicone rubber having a composition which varies according to the application. In short- or long-term thermal loading, for example in power hybrid systems, the proposed getters make it possible to intercept any corrosive fission products such as CO, CO.sub.2, NO/NO.sub.2, and water of reaction to avoid premature aging.

Abstract: A Zener diode (D) exhibiting subsurface breakdown includes a cathode (36) formed entirely within the emitter (22, 28) of a vertical PNP transistor (Q). The base (16) and collector (11) of the PNP transistor are resistively coupled to ground. The emitter of the PNP transistor functions as the anode of the Zener diode. Because of this, it is unecessary to provide an emitter contact. The PNP transistor compensates for changes in Zener breakdown voltage caused by changes in temperature. Because the PNP transistor is formed directly underneath the Zener diode, the temperature of the PNP transistor accurately tracks that of the Zener diode and therefore provides better temperature compensation. Also, because the cathode of the Zener diode is formed directly in the emitter of the PNP transistor, there is no lateral current flow and attendant voltage drop in the emitter of the PNP transistor.

Abstract: An electro-optical communication device which includes a light transmissive conduit integrally formed to interconnect a light emitter and a light detector. The length over which the light transmissive conduit extends is substantially greater than the size of either the light emitter or the light detector. In the preferred embodiment, the light emitter and the light detector are each formed from amorphous semiconductor alloy material and may be substantially surrounded by the light transmissive conduit.

Abstract: A power semiconductor module includes a multi-layered substrate formed of a first ceramic bottom plate, at least one second ceramic plate disposed above and parallel to the first ceramic bottom plate, a metal foil in the form of a textured metallization located between and directly bonded to the ceramic plates, the second ceramic plate having cutouts formed therein, and assembly elements soldered in the cutouts.

Abstract: A semiconductor device comprises a drain region, base regions, gate electrodes formed over the drain region between two adjacent base regions through an insulating layer such that each bridges the surface of the drain region to partially cover the two adjacent base regions, source regions provided in the base regions, a source electrode provided on the source regions, and a metal gate electrode wiring contacting the gate electrodes. The metal gate electrode wiring includes closed loop portions and the source electrode is divided into branch sections, each corresponding to the closed loop portion.

Abstract: A semiconductor integrated circuit device of the master slice type which is suitable for use both in digital and analog circuits. The device includes a plurality of parallel basic elements, each including a plurality of p channel MOS transistors having gate electrodes connected commonly and source and drain regions separated from each other and a plurality of n channel MOS transistors having gate electrodes connected commonly and source and drain regions separated from each other. The source and drain regions of the p and n channel MOS transistors arranged in corresponding positions of the basic elements are common.

Abstract: A field effect transistor utilizing semiconductor hetero junction having a high mutual conductance, low noise, and a reduced source resistance, has a gallium indium arsenide mixed crystal semiconductor layer (23) providing a current path, low resistance indium phosphide layers formed on or under the gallium indium arsenide mixed crystal semiconductor layer (23) by ion-implantation for achieving the reduced source resistance, a source electrode (6), a gate electrode (5) and a drain electrode (7) which are formed on the surface of an uppermost aluminum indium arsenide mixed crystal semiconductor layer (24), an ion-implanted layer located at least in a region to form the reduced source resistance between the source electrode (6) and a two-dimensional electron layer (8) within the gallium indium arsenide mixed crystal semiconductor layer (23).

Abstract: A semiconductor device comprises a semiconductor body having a surface provided with a first insulating layer. On this first insulating layer at least one pattern of conductor strips, coated with insulation strips having projecting edges, is provided. Under projecting edges of a second insulating layer, the conductor strips are coated with insulating tracks which fill the spaces under the edges and which at least at the area where they adjoin the first insulating layer can be selectively etched with respect to this layer. The conductor strips may be made of materials other than polycrystalline silicon, such as tungsten, molybdenum, and silicides of these metals. The thickness of the first insulating layer is affected to a very small extent during manufacture of the device, while its depth remains unchanged.

Abstract: A metal-semiconductor-metal photodiode comprises a semiconductor layer and a cathode electrode and an anode electrode which are formed on the semiconductor layer and are made of such mutually different electrode materials that the cathode electrode has a Schottky barrier height .phi..sub.bn from a conduction band satisfying .phi..sub.bn >Eg/2 and the anode electrode has a Schottky barrier height .phi..sub.bp from a valence band satisfying .phi..sub.bp >Eg/2, where Eg denotes the energy band gap.

Abstract: A circuit for protecting an input MOS FET (Q1) from electrostatic discharge pulses includes a plurality of diodes (D112a through D112f) coupled to the bonding pad (102) of an integrated circuit via a plurality of resistors (R110a through R110f). The resistors prevent excessive current from flowing through and hence damaging any of the diodes. The diodes possess a unique shape which maximizes the perimeter to surface area ratio and therefore permits more efficient energy dissipation along the periphery of the diodes. The diodes are adapted to break down in response to an excessive voltage at the bonding pad and therefor protect the gate structure of the input transistor. Also included in the circuit is a protective bipolar transistor (Q2) having a collector coupled to the bonding pad, an emitter coupled to ground and a base resistively coupled to ground.

Abstract: A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e.g., IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e.g.