Abstract: The present invention relates generally to a photodetector, and more particularly to a photodetector formed by a static induction transistor. The present invention includes the following constituent elements:In the photodetector formed by a static induction transistor, an n.sup.+ -type buried layer is provided, as a drain or source region of the photodetector, for limiting the thickness of a high resistivity i-type layer between a p.sup.+ -type region forming a gate and a substrate. Letting the wavelength of light incident to the surface of the photodetector and an absorption coefficient for the incident light be represented by .lambda..sub.i and .alpha..sub.i (.lambda..sub.i), respectively, the distance between the in junction of the abrupt pin junction and the surface of the photodetector x.sub.i is ##EQU1## the ratio between the area A(.lambda..sub.i) of each gate portion for selectively detecting light of the specified wavelength .lambda..sub.i and the total area A.sub.

Abstract: A voltage controlled oscillator includes a VCO chip that is a monolithic circuit with a Gunn diode and varactor diode intercoupled by a resonant circuit. A detector/discriminator/power divider chip is coupled to the VCO chip through a directional coupler and is a monolithic circuit having a pair of discriminator diodes and amplitude detector diode on a semi-insulating substrate with associated circuit components. Connected-together electrodes of the discriminator diodes are connected to one output of the power divider. An electrode of the amplitude detector diode is connected to the other output of the power divider. Stagger-tuned resonant circuits are coupled to the other electrodes of the discriminator diodes. Conducting portions forming low pass filters couple the amplitude detector diode and the discriminator detector diodes to respective outputs.

Abstract: In a solid-state image sensor of the type consisting of a semiconductor circuit substrate capable of charge transfer or having the switching function and a photoconductive layer or a photosensor, a pattern of light-shielding checks is formed between the surface of the semiconductor circuit substrate and a transparent electrode on the photoconductive layer or a photosensor so as to optically shield the gaps or spaces between electrodes which are provided for respective picture elements and which are connected to their associated diode regions and the photoconductive layer or photosensor, whereby blooming can be suppressed without causing a decrease in sensitivity.

Abstract: A high voltage semiconductor includes an electrically floating conductive layer located adjacent the field oxide in the gap region between a junction pair. The electrically floating conductive layer allows free charge in the insulating layers to be dissipated. As a result, the depletion region in the substrate is extended and the breakdown voltage of the device is improved considerably.

Abstract: A semiconductor device such as a solar cell, photodiode and solid state imaging device comprises a semiconductor layer made of amorphous silicon formed on a given substrate, and a transparent conductive layer formed by an interfacial reaction between the amorphous silicon and a metallic film directly formed on the amorphous silicon. This transparent conductive layer is used as a transparent electrode of the device and if necessary the remainder after having partially removed the metallic film for the transparent conductive layer is used as a conductive layer and right shielding film.

Abstract: A semiconductor device comprises two layers of semiconductor material each of different conductivity type, with a region of semiconductor material sandwiched between the layers. The material of which the region is formed is of the same composition as the first layer at the edge of the region adjacent to the first layer, and varies in composition linearly on the running average in the direction between the layers such that the region forms a heterojunction with the second layer.

Abstract: A semiconductor optical element having a layer which exhibits a function of diffraction grating between a first cladding layer and a second cladding layer, wherein the layer which exhibits the function of diffraction grating consists of a superlattice layer in which crystal layers are periodically mixed to constitute a semiconductor grating layer.

Abstract: A semiconductor device having a layer of semiconductor material disposed on an insulating substrate is disclosed. Source and drain depth extenders are provided within the semiconductor material for extending the respective source and drain regions to the insulating substrate. This device is fabricated in a manner which minimizes damage to the gate oxide layer that often occurs when high energy implants are used to form self-aligned source and drain regions.

Abstract: A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs.

Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

Abstract: An integrated transformer structure is disclosed. In one embodiment, the primary transformer winding is formed using dielectrically isolated (DI) technology so as to isolate high voltages applied to the transformer primary from other components in the substrate. Alternatively, conventional junction isolated technology may be used, where physical separation between the integrated transformer and other components may be provided. In accordance with the present invention, the primary winding comprises a planar spiral formed with a low-resistivity material and incorporated with the substrate. An insulating layer is then formed over the primary winding. A planar spiral configuration is also used to form the secondary winding, where the secondary may be formed of a deposited metal and is formed on top of the insulating layer so as to be directly above the primary winding. The result is an effective air-core transformer structure capable of isolating thousands of volts.

Abstract: Construction of a novel multilayer conductive interconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer which may be in contact with an underlying silicon substrate and comprising a material selected from the class consisting of TiW and TiN; an intermediate layer of conductive metal such as an aluminum base metal; and an upper barrier layer which may be in contact with a second aluminum base metal layer and which is selected from the class consisting of TiW, TiN, MoSi.sub.x and TaSi where x equals 2 or more.

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Abstract: A chip carrier for carrying integrated circuit chips is provided. Instead of placing individual circuit components either in the chips or next to them, the components are placed in or near the substrate of the chip carrier. This frees up expensive real-estate for logic chips at the chip level presently occupied by the components. The substrate of the carrier acts as a large heat sink to dissipate power generated by the components.

Abstract: A double barrier tunnel diode, wherein a central quantum well is disposed between a pair of barrier layers to form a quantum barrier, the barrier layers having a composition such that a resonance energy level is created in the quantum well layer, and having a thickness sufficiently small that electrons can tunnel through the quantum barrier under an applied voltage. The quantum well and barrier layers are disposed between two electron injection layers having compositions selected so that the conduction band minimum energy for electrons in the injection layers is about that of, but less than, the resonance energy level of the quantum well. Electrons pass through the quantum barrier by tunneling, upon application of a small voltage across the double barrier tunnel diode sufficient to raise electrons near the conduction band minimum energy of the injection layer to the resonance energy level of the quantum well.

Abstract: A high voltage semiconductor device includes a two-dimensional array of polygonal regions in a higher resistivity body portion of the opposite conductivity type. The p-n junction between these regions and the body portion may be, for example, a drain junction of a D-MOS transistor or a collector junction of a bipolar transistor and is reverse-biased in at least a high voltage mode of operation. In order to relieve the high electric field at the corners of the polygonal regions, a plurality of further regions is distributed in each area of the body portion between facing corners of three or more of the polygonal regions. These further regions of the same conductivity type as the polygonal regions are located on at least one line from each of these corners in a symmetrical arrangement of the further regions within each area.

Abstract: A vertical field effect transistor is provided which has its sources arranged in a pattern to essentially eliminate inactive common drain area between the sources. The preferred arrangement is to use rectangular source areas to form columns and rows in the arrangement. Every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row. The rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area. The elimination of inactive drain area results in low on resistance during the conductive state of the vertical field effect transistor.

Abstract: A method for compensating operationally-induced defects in a semiconductor device which includes a semiconductor body having opposed major surfaces and having first and second region therein. The method comprises determining the thickness of the second region by the energy level of the defects relative to the equilibrium Fermi level and introducing a compensating material into the second region. In the semiconductor device the thickness of the second region extends from a major surface to a position in the body at which the energy level of the defects is about equal to the equilibrium Fermi level. The semiconductor device is typically a photodetector comprising a first layer having a first conductivity type, the first region overlies the first layer and has an intrinsic conductivity type, the second region overlies the first region and has a conductivity type opposite to that of the first layer, and a second layer overlies the second region and has the same conductivity type of the second region.

Abstract: A strained layer superlattice comprising Ge.sub.x Si.sub.1-x layers interleaved with Si layers is an excellent photodetector at infrared wavelengths due to the large shift in bandgap caused by the strain in the superlattice.

Abstract: There is a conductivity modulated MOS transistor comprising: a p-type region formed in the surface area of an n.sup.- -type layer formed on a p.sup.+ -type layer; an n.sup.+ -type region formed in the surface area of this p-type region to face the n.sup.- -type layer; and a gate electrode formed through a gate insulation layer over a surface region of the p-type region sandwiched between the n.sup.- -type layer and the n.sup.+ -type region. This MOS transistor further comprises a p.sup.+ -type region formed inside the p-type region, at least under the n.sup.+ -type region and having a higher impurity concentration than the p-type region.