Abstract: A nonvolatile, EPROM type memory cell, formed using a p-channel MOS device instead of an n-channel MOS device as customary according to the prior art, offers several advantages: improved programming characteristics, a relatively low gate voltage for writing, a lower power dissipation and above all compatability with the great majority of CMOS fabrication processes. An explanation of such surprising characteristics may be attributed to more favorable conditions of electric field during programming, i.e. during charging of the floating gate, in respect to those existing in the case of the conventional n-channel memory cell.

Abstract: A semiconductor device in which two sorts of compound semiconductors having unequal lattice constants are joined, is disclosed.Defects such as dislocations attributed to lattice mismatching are avoided by subjecting one of the compound semiconductors to atomic layer doping with an impurity. Owing to this construction, it is permitted to combine the optimum materials as the compound semiconductors, and the semiconductor device has its performance improved and its design versatility expanded.

Abstract: A solid-state imaging device having a plurality of semiconductor layers of a first conductivity type for photo-electric conversion provided on the surface of a first semiconductor layer of a second conductivity type which is formed on a part of one surface of a semiconductor substrate of the first conductivity type, a semiconductor layer of the first conductivity type for charge transfer provided on the surface of a second semiconductor layer of the second conductivity type which is formed on a part of the surface of the substrate, and a signal output means. The first semiconductor layer of the second conductivity type and the second semiconductor layer of the second conductivity type are formed in different steps so that the first semiconductor layer is disposed deeper than the second semiconductor layer.

Abstract: A process for manufacturing a reprogrammable semiconductor memory device, such as EPROM, and its resulting structure is provided. A substrate has a main surface which is provided with grooves formed by etching. An oxide film is formed on the main surface and the side and bottom surfaces of each of the grooves. And, a first layer of doped polysilicon is formed on the oxide film, and the first layer of doped polysilicon is disconnected at the bottom of each of the grooves by selective removal thereof. A second layer of doped polysilicon is formed on the first layer of doped polysilicon with an inter-layer electrical insulator sandwiched therebetween. Thus, the first and second layers of polysilicon, together with the inter-layer insulator, define a stacked-gate electrode structure. A pair of source and drain regions is formed in the substrate one on each side of the stacked-gate electrode structure.

Abstract: A quantum well electron barrier diode comprising a substrate, a first buffer layer on the substrate, a superlattice structure on the first buffer layer, a second buffer layer on the superlattice structure, a contacting layer on the second buffer layer and first and second ohmic contacts attached to the contacting layer and substrate respectively. The superlattice structure comprises a sequence of a plurality of high energy gap barrier layers interleaved with a plurality of low energy gap wells. The sequence is repeated until the desired thickness is reached. Current flows perpendicular to the layers.

Abstract: A multilayer contact is shown in a heterojunction device. One contact extends through two or more vertical, conducting layers. Two contacts deposited on a common surface. Each contact separately bias different layers beneath the surface. A Schottky barrier between the contacts establishes a depletion region that electrically controls the current flow path between the contacts.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: A semiconductor device comprises a first semiconductor region having formed thereon a second semiconductor region which forms at its one surface an energy barrier with respect to minority carriers of the first semiconductor region, a conductive region in contact with the other surface of the second semiconductor region, and an induced layer formed in the operating state in a surface portion of the first semiconductor region in contact with the second semiconductor region under the conductive region, the carriers being transported across the induced layer to the first semiconductor region, whereby the conductive region acts as an emitter, the induced layer acts as a base and the first semiconductor layer acts as a collector of a transistor.

Abstract: An insulated gate device includes at least one cell having base and emitter region surfaces disposed in ohmic contact with a metallic emitter electrode. The cell is constructed to provide a larger ratio of base region surface area to emitter region surface area in contact with the emitter electrode than is found in the prior art. The cell is further constructed to provide paths for reverse current flow from a drift region through the base region and to the emitter electrode; these paths being spaced form the cell's emitter-base junction.

Abstract: In a lateral transistor having a first semiconductor region of one conductivity type, and an emitter region and a collector region both having the opposite conductivity type and disposed in the first semiconductor region; a second semiconductor region having the opposite conductivity type is disposed opposite to the emitter region with respect to the collector region. The thus obtained lateral transistor has a characteristic that a current flowing to the substrate is prevented under a saturation operation state and is suitably used to form, e.g., a current-mirror type constant-current circuit constituting a switching device having improved threshold characteristics.

Abstract: In a memory cell matrix region of a semiconductor memory device such as a dynamic RAM or a static RAM, wirings of the same material are distributed between different layers in such a manner that the upper wirings overlap the lower wirings. Accordingly, the width of the wirings can be increased for a semiconductor memory device having a high concentration and high integration.

Abstract: A semiconductor device includes a base semiconductor structure including semiconductor elements, interconnection layers for connecting the semiconductor elements together, and conductive pads to which the interconnection layers are connected, at least one stacking semiconductor structure including semiconductor elements, an interconnection layer for connecting the semiconductor elements together, and conductive pads to which the interconnection layers are connected, the stacking semiconductor structure having holes selectively formed therein to expose portions of the conductive pads, first conductive elements fixed in the holes of the stacking semiconductor structure, to be electrically connected to the exposed portions of the conductive pads, and second conductive elements fixed on the conductive pads of the base semiconductor structure, and fixed to the first conductive elements, with a gap provided between the base and stacking semiconductor structures.

Abstract: A method and an apparatus which permits use of a metal-insulator-semiconductor device as an infrared detector. A single layer of metal is provided having an extremely thin portion through which infrared radiation can pass and a thick portion through which infrared radiation cannot pass. Both of these portions together form the MIS (metal-insulator-semiconductor) gate. A voltage is applied to the metal which creates a potential well within the semiconductor substrate below. When the device is exposed to infrared radiation the radiation, causes photons to pass through the thin portion of the MIS gate and generates a charge within the potential well. The thick portion of the MIS gate shields the semiconductor substrate from photons so that no charges are generated in the potential well which is located below this portion of the metal layer. This provides a charge storage region so that the charge which is generated under the thin gate can be stored in the entire potential well created by the gate as a whole.

Abstract: A semiconductor device having a superlattice composed of two kinds of semiconductor materials, wherein the lattice unit of said superlattice is composed of periodically laminated layers consisting of four or more kinds of thin layers which are different from each other in the combination of materials and thickness.

Abstract: A lead frame for mounting a semiconductor chip in an integrated circuit package incorporates a deformation absorbing member as an integral part of the paddle support arm so that the initial, desired physical and electrical characteristics are unaltered after a forming operation such as paddle downsetting.

Abstract: By providing an intrinsic semiconductor region in a reverse biased junction cathode between an n-type surface region and a p-type zone, a maximum field is present over the intrinsic region in the operating condition. The efficiency of the cathode is increased because avalanche multiplication can now occur over a greater distance, while in addition electrons to be emitted at a sufficient energy are generated by means of tunneling.

Abstract: The ballast resistance of the base of a bipolar power transistor is realized by a localized pinching of the base region by means of a special diffused region. A surface metallization brings the diffused region into contact with the adjacent base region so that a diode is formed in parallel with the base ballast resistance. The diode becomes conductive when the voltage drop across the resistance which is generated by the base current of the transistor exceeds the conduction threshold of the junction, thereby bypassing the ballast resistance.

Abstract: A new solid state field effect bipolar device provides for high current gain and low input capacitance, while avoiding the "punch-through" effects that limit the downward scaling of conventional bipolar and field effect devices. The device typically comprises a metallic (e.g. a metal or silicide) emitter, which makes ohmic contact to a semi-insulator; a channel terminal which contacts an inversion layer formed at the interface between the semi-insulator and a semiconductor depletion region; and a collector, which is the semiconductor bulk. The novel device controls the flow of majority carriers from the emitter into the collector by the biasing action of charge in the inversion channel. The technique can be utilized in making a transistor, photodetector, thyristor, controlled optical emitter, and other devices.

Abstract: A field effect transistor comprises a source electrode, a drain electrode, a channel layer between the source electrode and the drain electrode, a gate electrode for controlling electric current in the channel layer, and a superlattice layer interposed between the channel layer and the gate electrode, the superlattice layer having a plurality of constituent thin layers perpendicular to a direction of electric current in the channel layer.

Abstract: The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a layer of recrystallized silicon as a second active region. A gate electrode overlies both active regions and serves as a mask to form in such respective regions self-aligned channels. The concentric placement of the active substrate monocrystalline silicon region, and inner perimeter of dielectric, and a further inner active region of recrystallized silicon situated over a dielectric region, facilitates recrystallization from seed of monocrystalline silicon irrespective of the direction of translation taken by the energy beam, and associated melt, in scanning across the structure.