Abstract: An MOS gate turn-off thyristor structure includes non-regenerative (three-layer or transistor) portions interspersed with the four-layer regenerative (thyristor) portions and further includes gate electrode segments disposed adjacent to relatively narrow portions of the base region. Upon application of an appropriate turn-off gate bias to the gate electrode segments, the base region of the regenerative portion in which they are disposed is pinched off and the current flowing therethrough is diverted to flow through the non-regenerative portion of the structure. This interrupts regeneration in the regenerative structure and the device turns off.

Abstract: A high electron mobility single heterojunction semiconductor devices having a layer configuration comprising a N-type AlGaAs layer grown on an undoped GaAs layer grown on an undoped AlGaAs layer grown on a semiconductor substrate containing an impurity producing a deep level. The undoped AlGaAs layer has at least three functions including (a) a getter for the deep level impurity which may be diffused from the substrate during an annealing process, (b) a buffer improving the crystal condition of the undoped GaAs layer, and (c) a test layer grown for the purpose of predetermining the intensity of molecular or ion beams for each of Al, Ga, As and dopants e.g. Si. This allows annealing processes and ion implantation processes to be introduced to the method for production of this type of semiconductor devices without reducing the electron mobility thereof.

Abstract: The invention is a semiconductor device assembly and method of making the same. A mounting plate has positioning means for positioning the plate relative to a header, a first mounting surface of the plate is attached to the header and a semiconductor device is attached to a second mounting surface of the mounting plate. The assembly is made by forming the mounting plate, positioning the mounting plate relative to the header by the positioning means, attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. Another method of making the assembly is by defining and etching a mounting plate and attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. This assembly and process provides an efficient means for mounting semiconductor devices and in particular electro-optic devices such as lasers.

Abstract: A two-terminal bidirectional semiconductor switching device comprising a body of silicon semiconductor material having in one portion a five-zone switching element and, in another portion integral therewith, a three-zone bidirectional voltage-sensitive breakdown element, there being means including another portion of the body connecting the three-zone element as a gating element to said five-zone element so as to trigger conduction therein bidirectionally when voltage breakdown occurs in either direction in the three-zone element.

Abstract: A static memory cell including a pair of field-effect transistors, characterized by the provision of highly dielectric layers in combination with the field-effect transistors, wherein each of the highly dielectric layers is located directly on a polysilicon gate electrode layer formed on a silicon dioxide insulating layer bridging the channel region of each of the field-effect transistors. The gate electrode layer of one field-effect transistor is held in direct contact with the drain region of the other field-effect transistor and the two highly dielectric layers are covered with a polysilicon conductive layer electrically connected to a supply voltage source so that each field-effect transistor has its drain region connected to the supply voltage source through one dielectric layer and its gate electrode layer connected to the voltage source through the other dielectric layer.

Abstract: A semiconductor device which utilizes the fact that the effective mass of charged particles becomes exceedingly large at certain points in the direction of a periodically repeating potential by virtue of a periodic structure in which semiconductor layers are stacked in the form of a superlattice. The periodic structure enables the movement of charged particles to be one-dimensional and thus permits a great improvement in the mobility of charged particles in the channel direction. Accordingly, it is possible to realize a FET of ultrahigh mobility.

Abstract: A thermally stable low resistance ohmic contact to gallium arsenide is fabricated using a layer of refractory material, and a layer of indium and a metal which forms thermally stable intermetallic compounds or single solid phase with indium. In forming the contact, a layer of indium is sandwiched between two layers of nickel, the sandwiched array of layers sitting on the substrate with the refractory tungsten layer on top to form a stratified structure. The stratified structure is heated to form nickel and indium intermetallic compounds and InGaAs layer at the metal/semiconductor interface. A thin layer of nickel between the indium and the gallium arsenide tends to form intermetallic compounds and limit a rate of diffusion of the indium into the gallium arsenide during heating so as to form a uniform fine distribution of InGaAs layer at the metal/gallium arsenide interface which results in low contact resistance. A contact resistance of 0.

Abstract: A ferrite shield component for suppressing high frequency signals in electrical circuits, such as tuners for television receivers, is formed by surrounding an electrical conductor with ferrite material. The shield component is formed in the shape of a leadless chip to permit placement on a circuit board by chip insertion machines. The conductor pattern and ferrite material may be selected to determine particular impedance-frequency characteristics.

Abstract: A semiconductor device having a plurality of laminated semiconductor layers in which a current flows in the direction of lamination. A superlattice layer is formed in at least one of the layers and the potential of the quantum well of the superlattice layer is lower than the potential of the semiconductor layer in which the superlattice layer is formed. The potential of the barrier of the superlattice layer is higher than the potential of the semiconductor layer in which said superlattice layer is formed.

Abstract: A semiconductor device is disclosed with a conductive on-chip shield film formed on its surface. The on-chip shield film is patterned in a manner substantially complementary to the pattern of the wiring layer of the semiconductor device so that the shield film does not cover portions of the semiconductor device which are covered by the wiring-pattern layer. In this manner, the on-chip shield film of the semiconductor device provides high resistance to electrostatic and electromagnetic induction while maintaining the ability of the device to withstand changes in ambient temperature.

Abstract: An electronic assembly having a semiconductor device back bonded to a first lead frame. An adhesive insulative tape is placed on the first lead frame and the device. A second lead frame is mounted on the adhesive tape. Electrical contacts by wire bonds are established between the device and the first and second lead frames.

Abstract: A semiconductor switch circuit of field-drive type includes a bipolar component having forward blocking and reverse blocking junctions, and p-channel and n-channel IGPETS connected across the bipolar component so as to short-circuit its forward blocking junction. The switch circuit operates to turn on or off in response to the voltage signal to the gate circuit which is isolated from the bipolar component, irrespective of the polarity of a voltage applied across the bipolar component.

Abstract: A heavily doped P region is formed at the end of a lightly doped P- drain extension adjacent to the channel of a P channel MOS transistor. If the PMOS transistor is fabricated in an N-well surrounded by P- type material, a parasitic vertical transistor is formed which may be undesireably biased into its active mode if the voltage at the P+ drain of the PMOS transistor causes the P+ drain and N- body to be forward biased. When this vertical transistor conducts, power is wasted. The addition of the P region formed at the end of the lightly doped drain greatly increases the current gain of the parasitic lateral transistor, which is biased into its active mode under the same conditions which bias the vertical transistor into its active mode.

Abstract: A disclosed MOSFET cell has a source region formed at the top surface of a semiconductor substrate. The top surface source region is electrically coupled to a conductive region at a bottom portion of the substrate by means of a vertical conduit which projects through the substrate from the top surface to the conductive region. A current exchanger is provided extending over the top surface of the substrate and coupling a top surface portion of the vertical conduit to the source region. The current exchanger makes ohmic contact with the source region and with the conduit region and shorts the two regions together such that majority carrier current of the conduit region will be "converted" into majority carrier current of the source region and electrical continuity between the source region and the conductive region of the substrate is established.

Abstract: A semiconductor device, e.g. a photoelectric converter, comprises a semiconductor transistor having a semiconductor controlling electrode region of one conductivity type resettable at a desired stage, an element isolation region of the same conductivity type, and an insulated gate type switching transistor for making the controlling electrode region and the element isolation region electrically conductive with each other. The element isolation region is preferably formed by at least two impurity injections with lamination or superposition. A peripheral element may be provided in the same substrate simultaneously with the formation of the semiconductor transistor and the element isolation region.

Abstract: A DRAM memory cell has a trench capacitor and a transistor. The trench of the trench capacitor penetrates to a buried layer which acts as the primary portion of one of the plates of the capacitor. When the buried layer is the same conductivity type as the transistor of the memory cell, the buried layer is biased to a voltage selected to reduce the maximum voltage across the capacitor. This allows for a reduction in the thickness of the dielectric which coats the trench which increases the capacitance of the capacitor. When the buried layer is of the opposite conductivity type from the transistor type of the memory cell, there is no parasitic MOS transistor formed between the primary portion of the capacitor plate and the source of the transistor of the memory cell.

Abstract: A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+-P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy.

Abstract: In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents minority carries in each of the paired bases from diffusing into an adjacent base, and thus, prevents influence between the paired memory cells. The base contact region may be isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block composed of the paired cells and the base contact region is isolated at its circumference by the narrow groove.

Abstract: In a gate turn-off thyristor including two separate gate electrodes, a first turn-off gate signal is applied to the first gate electrode and then a second turn-off gate signal is applied to the second gate electrode after a predetermined time has elapsed in order to improve the controllable anode current and to improve the capability against an anode-voltage rising rate. This is because the flow distribution of the anode current is unbalanced asymmetrical with respect to the structural center of the GTO and therefore the internal resistance between the cathode K and the second gate G.sub.2 is reduced, so that it is possible to increase the magnitude of the turn-off gate current near the time when the anode current drops sharply or at the end of the GTO switching off operation.

Abstract: A plastic semiconductor package suitable for high frequency operation includes an internal ground plane connected to a ground ring formed on the packaged semiconductor device. The ground plane is included as a portion of a lead frame strip adjacent to the individual lead frames. The ground plane is first folded underneath the paddle support of the lead frame, and the semiconductor die subsequently mounted on the paddle. The ground plane includes a plurality of bumps which protect upward between adjacent lead fingers of the lead frame when the ground frame is folded. A ground frame on the semiconductor die is connected to the bumps, and the signal bonding pads connected to the lead fingers, typically by wire or tape bonding. The package is then encapsulated in plastic by conventional means, and the package trimmed to its final desired configuration.