Patents Examined by Marwan Ayash
  • Patent number: 9767027
    Abstract: A system for optimizing cache coherence message traffic volume is disclosed. The system includes a plurality of caches in a multi-level memory hierarchy and a plurality of agents. Each agent is associated with a cache. The system includes one or more monitoring engines. Each agent in the plurality of agents is associated with a monitoring engine. The agents can execute a processor level software instruction causing a memory region to be private to the agent. Each of the agents is configured to execute a memory access for data on an associated cache and to send a request for data up the hierarchy on a cache miss. The monitoring engine is configured to intercept request for data from an agent and to prevent snooping for the cache line in peer caches when the cache line associated with a memory region represented as private to the agent.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 19, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jan Gray, David Callahn, Burton Jordan Smith, Gad Sheaffer, Ali-Reza Adl-Tabatabai
  • Patent number: 9715434
    Abstract: Techniques for data migration of a storage system are described herein. According to one embodiment, for at least one of segments of a file to be migrated from a source storage tier to a target storage tier, a fingerprint of the segment is transmitted to the target storage tier. In response to a response received from the target storage tier indicating that the segment has not been stored in the target tier based on the fingerprint, a storage space of the target tier estimated for migrating the file is incremented. One or more segments of the file that have not been stored in the target tier are migrated if the one or more segments of the file fit in the target storage tier based on the estimated storage space of the target tier.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 25, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Teng Xu, Windsor W. Hsu, Lan Chin
  • Patent number: 9710198
    Abstract: The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: July 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Robert S. Wu, Jian Chen, Ashish Karkare, Alon Marcu, Vsevolod Mountaniol
  • Patent number: 9684471
    Abstract: Various embodiments for priority based depopulation of ranks in a computing storage environment are provided. In one embodiment, a method comprises prioritizing a plurality of ranks selected for depopulation. Highest priority and lowest priority ranks are marked and selected for depopulation. Lower priority ranks are placed in a queue in order of priority. An extent of one of the lower priority ranks is migrated to a rank not selected for depopulation. One of the lower priority ranks with newer data is selected for executing a read operation in response to a read operation to one of the lower priority ranks. At least one of the highest priority ranks is depopulated to at least one of a plurality of targeted ranks. The highest priority rank is left as unassigned to one of the plurality of targeted ranks until determining if the highest priority rank is to be assigned the targeted ranks.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juan A. Coronado, Jennifer S. Shioya, Todd M. Tosseth
  • Patent number: 9665291
    Abstract: A method and an apparatus for tiered storage processing of data, and a storage device. The method includes: splitting the migration unit into multiple migration subunits when a migration unit of low-tier disks is migrated to high-tier disks, and detecting a data access frequency of each migration subunit respectively; migrating the migration subunit to the low-tier disk when detecting that the data access frequency of the migration subunit is lower than a set threshold; and combining the multiple migration subunits into the migration unit when detecting that the multiple migration subunits are all migrated to the lower-tier disk. The present invention improves usage of storage media, and controls metadata storage resource consumption effectively.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: May 30, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yu Lin, Shangdong Liang
  • Patent number: 9652335
    Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 16, 2017
    Assignee: Commvault Systems, Inc.
    Inventors: Duncan Littlefield, Ho-chi Chen, Rajiv Kottomtharayil
  • Patent number: 9639465
    Abstract: A method and apparatus for controlling a frequency of CMI are disclosed. The method may include classifying request types into one or more request groups, wherein each of the request types is a type of CMI request. A number of clock cycles that is sufficient to process a request in each request group may be assigned, and requests that are made to CMI may be monitored with one or more performance counters. A number of requests that occur during a length of time in each request group may be determined, and a frequency of the CMI may be periodically adjusted based upon the number of requests occurring per second in each request group and the assigned number of clock cycles per request for each request group.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: May 2, 2017
    Assignee: Qualcomm Innovation Center, Inc.
    Inventor: Saravana Krishnan Kannan
  • Patent number: 9601180
    Abstract: Methods of configuring dynamic memory associated with a processing system, are described. The dynamic memory is configured in a plurality of blocks, the method comprises: a) receiving information relating to a utilization status of the memory; b) processing the received information to determine at least one first block of the memory that is currently not in use for information storage; and c) configuring the at least one first block to be excluded from an information refresh process.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: March 21, 2017
    Assignee: Optis Circuit Technology, LLC
    Inventors: Maxime Coquelin, Loic Pallardy
  • Patent number: 9563383
    Abstract: The primary storage sub system writes a marker that includes the sequence number and that indicates a completion of the data copy into the journal storage area of the first primary group when the data copy from a first primary data volume to a second primary data volume is completed. The primary storage sub system transmits a journal of the first primary group to a first secondary group corresponded to the first primary group and transmits a journal of a second primary group to a second secondary group corresponded to a second primary group.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: February 7, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Azusa Jin, Tomohiro Kawaguchi, Hideo Saito, Akira Deguchi, Tomohiro Yoshihara
  • Patent number: 9547444
    Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: January 17, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xueshi Yang, Chi Kong Lee
  • Patent number: 9542312
    Abstract: Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: January 10, 2017
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Xueshi Yang, Tony Yoon
  • Patent number: 9519438
    Abstract: Technologies are described for implementing a migration mechanism in a storage system containing multiple tiers of storage with each tier having different cost and performance parameters. Access statistics can be collected for each territory, or storage entity, within the storage system. Data that is accessed more frequently can be migrated toward higher performance storage tiers while data that is accessed less frequently can be migrated towards lower performance storage tiers. The placement of data may be governed first by the promotion of territories with higher access frequency to higher tiers. Secondly, data migration may be governed by demoting territories to lower tiers to create room for the promotion of more eligible territories from the next lower tier. In instances where space is not available on the next lower tier, further demotion may take place to an even lower tier in order to make space for the first demotion.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 13, 2016
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Ajit Narayanan, Loganathan Ranganathan, Sharon Enoch
  • Patent number: 9519583
    Abstract: The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: George L. Chiu, Alexandre E. Eichenberger, John K. P. O'Brien
  • Patent number: 9519599
    Abstract: A memory location determining device determines memory locations for storing M pieces of compressed data each of which is compressed from one of M pieces of N-bit data. For each piece of compressed data, the memory location determining device performs a first arithmetic operation on an address value of a corresponding piece of N-bit data, and determines to store X bits of the piece of compressed data and a flag indicating whether or not the piece of compressed data exceeds X bits at a location indicated by the result value of the first arithmetic operation. When the piece of compressed data exceeds X bits, the memory location determining device further performs a second arithmetic operation on the address value of the corresponding piece of N-bit data and determines to store one or more bits of the piece of compressed data other than the X bits.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 13, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shinya Matsuyama
  • Patent number: 9507702
    Abstract: A flash memory storage device, a controller thereof, and a programming management method thereof are provide for the flash memory storage device including a flash memory chip, wherein at least a first thread and a second thread are to be implemented within the flash memory storage device. The method includes defining a predetermined programming unit and receiving a first write command sent by a host. The method also includes distributing a control right of the flash memory chip to the first thread if the first write command is determined to be executed by the first thread, and controlling the first thread to release the control right of the flash memory chip after the first thread finishes a programming operation of the predetermined programming unit.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: November 29, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ching-Wen Chang
  • Patent number: 9483358
    Abstract: A method, article of manufacture, and apparatus for protecting data. In some embodiments, this includes identifying a parent virtual container, identifying a linked child virtual container, creating a fast copy of the parent virtual container and the linked child virtual container, and consolidating the copy of the parent virtual container and the copy of the linked child virtual container based on the format of the parent virtual container.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 1, 2016
    Assignee: EMC IP Holding Company LLC
    Inventors: Shankar Balasubramanian, Vladimir Mandic, Sriprasad Bhat Kasargod, Anand Raj
  • Patent number: 9454306
    Abstract: Workload on an aggregation of storage devices can be quantified in terms of demand on the aggregation of storage devices and demand on logical storage containers configured on the aggregation of storage devices. The demand on the aggregation of storage devices and the demand on logical storage containers thereon are calculated in a manner that captures demand on both storage capacity and performance capability. Capturing demand on both storage capacity and performance capability facilitates intelligent management that accounts for the relationship between storage capacity and performance capability. This allows the owner/operator of the storage equipment to use storage capacity at a desired (or requested) performance.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: September 27, 2016
    Assignee: NETAPP, INC.
    Inventors: Lewis R. Newby, Jr., Kelly Hemphill
  • Patent number: 9442845
    Abstract: The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 13, 2016
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chunlei Fan, Wenhua Du, Zixue Bi
  • Patent number: 9400608
    Abstract: Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Amit, Ori Shalev
  • Patent number: 9400803
    Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: July 26, 2016
    Assignee: Commvault Systems, Inc.
    Inventors: Duncan Littlefield, Ho-chi Chen, Rajiv Kottomtharayil