Abstract: A display device includes a display region including light emitting elements; a first inorganic insulating layer covering the light emitting elements; a first organic insulating layer on the first inorganic insulating layer; a second organic insulating layer on the first organic insulating layer; a third organic insulating layer on the second organic insulating layer; and a second inorganic insulating layer on the third organic insulating layer. Edges of the first to third organic insulating layers are between edges of the first and second inorganic insulating layers and an edge of the display region; the edge of the second organic insulating layer is between the edge of the first organic insulating layer and the edge of the display region; and the edge of the third organic insulating layer is between the edges of the first and second inorganic insulating layers and the edge of the second organic insulating layer.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

Abstract: A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution structure is embedded in the molding layer with a surface exposed by the molding layer. The build-up structure is formed on the bottom surface of the molding layer. An inner stress caused by a CTE difference between different materials in the package substrate is reduced by forming at least one groove which is arranged around the periphery of the redistribution structure onto the top surface of the molding layer, thereby improving the problem of the redistribution structure cracking in the prior art.

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Abstract: Provided are a light emitting device having a nitride quantum dot and a method of manufacturing the same. The light emitting device may include: a substrate; a nitride-based buffer layer arranged on the substrate; a plurality of nanorod layers arranged on the nitride-based buffer layer in a vertical direction and spaced apart from each other; a nitride quantum dot arranged on each of the plurality of nanorod layers; and a top contact layer covering the plurality of nanorod layers and the nitride quantum dots. A pyramid-shaped material layer may be further included between each of the plurality of nanorod layers and each of the nitride quantum dots. One or the plurality of nitride quantum dots may be arranged on each of the nanorod layers.

Abstract: A flexible lighting element is provided, comprising: a first substrate; first and second conductive elements over the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first and second contacts being electrically connected to the first and second conductive elements, respectively, and the light-emitting element emitting light from a second surface opposite the first surface; a transparent layer located adjacent to the second surface; and a transparent affixing layer located between the first substrate and the transparent layer, wherein the transparent layer and the transparent affixing layer are both sufficiently transparent to visible light that they will not decrease light transmittance below 70%, and the first and second conductive layers are at least partially transparent to visible light, or are 300 ?m or smaller in width, or are concealed by a design feature from a viewing direction.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region using an oxide semiconductor layer, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer.

Abstract: An array substrate and a manufacturing method thereof are provided. The method for manufacturing the array substrate includes: forming a passivation layer on a base substrate; forming photoresist on the passivation layer, and forming a first photoresist pattern including a photoresist-completely-retained region, a photoresist-partially-retained region and a photoresist-completely-removed region, by exposure and development processes; forming a first through hole in the passivation layer by etching the passivation layer with the first photoresist pattern as a mask; forming a second photoresist pattern by performing ashing on the first photoresist pattern to remove the photoresist in the photoresist-partially-retained region and reduce a thickness of the photoresist in the photoresist-completely-retained region; and etching the passivation layer with the second photoresist pattern as a mask, so as to reduce a thickness of the passivation layer in the photoresist-partially-retained region.

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

Abstract: Described herein are compositions and methods using same for forming a silicon-containing film or material such as without limitation a silicon oxide, silicon nitride, silicon oxynitride, a carbon-doped silicon nitride, or a carbon-doped silicon oxide film in a semiconductor deposition process, such as without limitation, a plasma enhanced atomic layer deposition of silicon-containing film.

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Abstract: First irradiation which causes an emission output from a flash lamp to reach its maximum value over a time period in the range of 1 to 20 milliseconds is performed to increase the temperature of a front surface of a semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. This achieves the activation of the impurities. Subsequently, second irradiation which gradually decreases the emission output from the maximum value over a time period in the range of 3 to 50 milliseconds is performed to maintain the temperature of the front surface within a ±25° C. range around the target temperature for a time period in the range of 3 to 50 milliseconds. This prevents the occurrence of process-induced damage while suppressing the diffusion of the impurities.

Abstract: Embodiments are related generally to electronic displays and, more particularly, to emissive displays made with transparent sheets having phosphor dots on the surface for the purpose of color conversion.

Abstract: An organic semiconductor crystalline film and weak oriented epitaxy growth preparation method thereof. The organic semiconductor crystalline film is a n-type semiconductor or a p-type semiconductor, and organic semiconductor crystal molecules in the organic semiconductor crystalline film are oriented in a stand-up manner on the ordered substrate, and have an oriented relationship with the ordered substrate. The organic semiconductor crystalline film prepared by the present invention is useful for organic transistor and organic phototransistor devices. The method of the present invention can control the high carrier mobility direction of organic semiconductor crystals to have ordered orientation in the film, enhance contacts between crystals, improve mechanical strength and micro-machining property of the film, and give a high carrier mobility. The carrier mobility of weak oriented epitaxially grown film of the present invention is 0.