Abstract: The invention comprises a solid state infrared source apparatus and method of use thereof, comprising: (1) an electrically conductive film comprising: an emission side and a back side opposite the emission side and a surface area to height ratio of at least five hundred to one; (2) a first dielectric film contacting the back side of the electrically conductive film; and (3) a reflective layer, the reflective layer embedded in the solid state source between the first dielectric film and a support layer, wherein the electrically conductive film emits infrared light upon warming with an electrical current during use, the infrared light sequentially reflecting off of the reflective layer, transmitting through the electrically conductive film, and emitting from the solid state source. Preferably the electrically conductive film comprises zinc oxide and the reflective layer is deposited into a basin in a second dielectric film.

Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode.

Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin. The method includes preparing a wiring board in which upstanding encircling walls with side-surface shield layers embedded therein surround mounts on which semiconductor chips are to be mounted, mounting the semiconductor chips on the mounts surrounded by the upstanding encircling walls on the wiring board, supplying a sealing synthetic resin to spaces surrounded by the upstanding encircling walls thereby to produce an sealed board, dividing the sealed board along projected dicing lines into individual semiconductor packages, and forming an upper-surface shield layer for blocking electromagnetic waves on the semiconductor packages.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

Abstract: A light emitting device and light emitting module using the same are provided. The light emitting device includes a substrate, a light-emitting element provided on the substrate, and a light transmissive sealing member covering the light-emitting element on the substrate. The light transmissive sealing member includes a body portion and a lens portion that are sequentially disposed from a substrate side.

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract: A TFT is disclosed. An anti-damage layer is arranged between an active layer and a source of the TFT, and the anti-damage layer is arranged between the active layer and a drain of the TFT. According to the present disclosure, the TFT has a simple structure. Through arranging the anti-damage layer between the active layer and the source of the TFT and between the active layer and the drain of the TFT, the length of the channel can be effectively reduced, and the parasite capacitor between the source and the gate of the TFT and between the drain and the gate of the TFT can be reduced.

Abstract: First, second, and third integrated devices each include one or more interconnecting structure. Each interconnecting structure includes (i) one or more interconnecting nodules extending from an edge surface of the device, (ii) one or more interconnect voids formed in an edge surface of the device, or (iii) both (i) and (ii). The one or more interconnecting structures on each of the first and second device is mated with the one or more interconnecting structures on the second device. The first integrated device includes a signal output, the third integrated device includes a signal input; and the second integrated device includes a conductor for conducting a signal from the signal output to the signal input.

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method comprises: forming a first gate metal pattern on a base substrate; forming a gate insulating layer, a first active layer pattern and a source-drain metal pattern on the base substrate on which the first gate metal pattern is formed; forming a first protective layer pattern and a through hole pattern on the base substrate on which the source-drain metal pattern is formed; and forming a second active layer pattern and a pixel electrode pattern on the base substrate on which the first protective layer pattern is formed. Embodiments of the present disclosure solve problems of poor display performance and high cost of the array substrate and achieve effects of improving the display performance and reducing the cost.

Abstract: A vertical light-emitting diode device and a method of fabricating the same are provided. The device may include a conductive substrate serving as a p electrode, a p-type GaN layer provided on the conductive substrate, an active layer provided on the p-type GaN layer, an n-type GaN layer provided on the active layer, an n electrode pattern provided on the n-type GaN layer, a metal oxide structure filling a plurality of holes formed in the n-type GaN layer, and a seed layer provided on bottom surfaces of the holes and used to as a seed in a crystal growth process of the metal oxide structure.

Abstract: Related to is the technical field of display panels, and in particular to a thin film transistor and a method for manufacturing the same. The thin film transistor provided on a substrate includes a drain, a source, a gate, and an active layer. The drain and the source are in a comb-like shape and are connected with the active layer through a first via hole and a second via hole, respectively. Such arrangement enables a width of a channel formed between the drain and the source to be increased and a layout scale of the thin film transistor to be reduced at the same time, whereby space is saved. When used in a GOA circuit or other circuits, the thin film transistor is helpful to achievement of a narrow-bezel design of a display panel.

Abstract: A semiconductor light emitting diode is disclosed. The semiconductor light emitting diode includes a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a transparent electrode formed on the second conductive semiconductor layer, a non-conductive reflection film covering the circumferential surface of the transparent electrode and having one or more via-holes formed therein, a reflective electrode formed on the non-conductive reflection film, interconnection electrodes filled in the via-holes and electrically connecting the reflective electrode to the transparent electrode, and ohmic contact layers formed between the transparent electrode and the interconnection electrodes and filled in recesses formed at positions of the transparent electrode corresponding to the via-holes by etching or extending through the via-holes from the recesses.

Abstract: A method and device for coating projecting surfaces of discrete projections of a product substrate that has functional units arranged at least partially in recesses. The method includes the steps of: bringing the projecting surfaces into contact with a coating material that is applied on a carrier substrate, and separating the carrier substrate from the projecting surfaces in such a way that the coating material remains partially on the product substrate. In addition, this invention relates to a corresponding device.

Abstract: A resist underlayer film-forming composition for lithography process having characteristics of enabling wafer surface planarization after film formation, excellent planarization performance on substrate with level difference, and good embeddability in fine hole pattern. The resist underlayer film-forming composition including polymer having unit structure of Formula (1) and solvent, wherein each of R1 to R4 is independently hydrogen atom or methyl group, and X1 is divalent organic group having at least one arylene group optionally substituted by alkyl group, amino group, or hydroxyl group, and wherein X1 in Formula (1) is organic group of Formula (2), wherein A1 is phenylene group or naphthylene group, A2 is phenylene group, naphthylene group, or organic group of Formula (3), and dotted line is bond, and wherein each of A3 and A4 is independently phenylene group or naphthylene group, and dotted line is bond.

Abstract: A light-emitting diode substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a light-emitting diode (LED) substrate, including: disposing a supporting substrate supporting a plurality of LED units to be opposed to a receiving substrate so that a side of the supporting substrate facing the receiving substrate supports the plurality of LED units; and irradiating a side of the supporting substrate away from the receiving substrate with laser, stripping the LED units from the supporting substrate, and transferring the LED units onto the receiving substrate. The manufacturing method of the LED substrate can better transfer LED units from the supporting substrate onto the receiving substrate.

Abstract: A light-emitting device package of the embodiments includes a package body; at least one light emitting device above the package body; an adhesive layer between the at least one light emitting device and the package body; and an adhesive-layer-accommodating portion disposed in the package body for accommodating the adhesive layer therein, wherein the adhesive-layer-accommodating portion has a side surface disposed to be inclined at a predetermined angle relative to an imaginary vertical plane that extends in a thickness direction of the package body.