Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Abstract: A pixelated-LED chip includes an active layer with active layer portions, segregated by streets, that are configured to illuminate different light-transmissive substrate portions to form pixels. A light extraction surface of each substrate portion includes protruding features and light extraction surface recesses that may be formed by sawing. Underfill material may be provided between a pixelated-LED chip and a mounting surface, as well as between pixels and between anodes and cathodes thereof. Certain implementations provide light extraction surface recesses that are non-parallel to each street defined through the active layer. Certain implementations provide light extraction surface recesses that are non-aligned with (e.g., non-parallel to) anode-cathode boundaries of each anode-cathode pair. Such arrangements reduce a likelihood of cracking in portions of a pixelated-LED chip. Methods for fabricating pixelated-LED chips are also provided.

Abstract: An optical device includes a multilayered GaAs structure including a plurality of sublayers and an optical structure layer on the multilayered GaAs structure, the optical structure layer including a Group III-V compound semiconductor material. The optical structure layer may be, for example, a light-emitting layer having a multi-quantum well structure.

Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A light-emitting element includes a semiconductor layered body including an n-side semiconductor layer having a first region and second regions, a p-side semiconductor layer on the first region, and a light-emitting layer between the first region and the p-side semiconductor layer; an insulating film defining at least one p-side opening above the p-side semiconductor layer and n-side openings each defined above a corresponding second region; an n-side electrode connected to each second region at each corresponding n-side opening; and a p-side electrode electrically connected to the p-side semiconductor layer through the p-side opening. In a top view, the n-side electrode includes at least one base portion on the first region, at least one first extending portion extending in a first direction from the base portion, and at least one second extending portion extending in the first direction from the base portion.

Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

Abstract: A quantum dot device includes: a first electrode and a second electrode facing each other; a quantum dot layer between the first electrode and the second electrode, and an electron auxiliary layer between the quantum dot layer and the second electrode, the electron auxiliary layer including a first nanoparticle and a second nanoparticle which is larger than the first nanoparticle, wherein a work function of the first electrode is greater than a work function of the second electrode, and wherein a difference between a lowest unoccupied molecular orbital energy level of the quantum dot layer and a lowest unoccupied molecular orbital energy level of the electron auxiliary layer is less than about 1.1 electronvolts.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.

Abstract: A micro light-emitting device, including a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first type electrode, a second type electrode, and a light reflection layer, is provided. The light-emitting layer is arranged on the first type semiconductor layer. The second type semiconductor layer is arranged on the light-emitting layer. The first type electrode and the second type electrode are both arranged on the second type semiconductor layer. The light reflection layer is arranged between the light-emitting layer and the first type electrode. The light reflection layer includes an oxidized area and a non-oxidized area. A reflectance of the oxidized area is greater than a reflectance of the non-oxidized area. An orthographic projection of a part of the oxidized area on the first type semiconductor layer and an orthographic projection of the first type electrode on the first type semiconductor layer at least partially overlap.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a substrate, an isolation structure over the substrate, a fin extending from the substrate, and an epitaxial feature over the fin. The epitaxial feature comprises a lower portion and an upper portion. The lower portion extends from the fin and extends above the isolation structure. The upper portion is over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to a lengthwise direction of the fin.

Abstract: A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.

Abstract: In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Abstract: A method for manufacturing a substrate comprising the following steps of: providing a stack comprising an initial substrate, a GaN layer, a doped InGaN layer and an unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to an anodising support, so as to form a second stack, dipping the second stack and the counter-electrode into an electrolyte solution, and applying a voltage or current between the doped InGaN layer and a counter electrode, to porosify the doped InGaN layer, and relaxing the unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to a support of interest, forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: An ESD protection device (100) is disclosed. More particularly, the ESD protection device is configured so that a gate electrode (140) and a capacitor electrode (170) electrically connected to a drain region (162) are spaced apart from each other by a preset distance, and partially or entirely overlap each other, thereby increasing a capacitance (Cgd) between the gate electrode and the drain region.

Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.