Abstract: A display apparatus includes a display panel including a plurality of pixels, and a cover panel including a window layer, an optical filter layer, a color filter layer and a bezel layer. The window layer includes a transmission region and a bezel region adjacent to the transmission region. The optical filter layer is disposed on the transmission region of the rear surface of the window layer. The color filter layer is disposed on the optical filter layer and includes a quantum dot. The bezel layer is disposed on the bezel region of the rear surface. The optical filter layer includes a partition wall layer, in which an opening is defined, a light-blocking layer disposed on the partition wall layer, and a reflection layer disposed in the opening. The bezel layer has a same color as the light-blocking layer.

Abstract: A semiconductor wafer, a bonding structure, and a wafer bonding method are provided. In the semiconductor wafer, a bonding pad which is electrically connected to the interconnection structure is formed in the top cover layer, and a bonding alignment mark formed by a point array is disposed in the top cover layer. In this way, the bonding alignment mark is disposed in the top cover layer, and the top cover layer is not covered by another material layer, thereby facilitating recognition of the alignment pattern by the bonding device and increasing the alignment window in bonding process. Moreover, the bonding alignment mark is formed by a point array, thereby facilitating integration of the process for forming the bonding alignment mark with the bonding hole process and avoiding defects such as the dishing phenomenon in the manufacturing process.

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract: A device includes a particle propagation channel, a particle deflector, a particle source, and a particle sink. The particle deflector facilitates ballistic transport of particles from a particle inflow portion through a particle flow deflection portion to a particle outflow portion. The particle deflector is arranged at the particle flow deflection portion and is activatable to deflect particles in the flow deflection portion and is configured to selectively prevent the particles from reaching the particle outflow portion. The particle source and particle sink are configured to cause a current path of the particles through the device.

Abstract: A display panel and fabrication method, and a display device are provided. The display panel includes a base substrate, a first transistor and a storage capacitor. The storage capacitor includes a first electrode and a second electrode, and the first electrode and a gate of the first transistor have an overlapped region. The display panel also includes a first insulating layer having a plurality of first vias in the overlapped region, and the first electrode is electrically connected to the gate of the first transistor through the plurality of first vias. A plurality of grooves are formed on a side of the first electrode facing away from the base substrate. A plurality of protrusions are formed on a side of the second electrode facing toward the base substrate. A groove, a protrusion and a first via overlap in a direction perpendicular to the surface of the base substrate.

Abstract: A biosensor comprising a substrate, a gate electrode provided on the substrate, an insulating layer provided on the gate electrode, a source electrode and a drain electrode, provided on the insulating layer, respectively, an n-type channel provided between the source electrode and the drain electrode, and a quantum dot layer provided on the n-type channel and provided so as to have electronic transition energy capable of resonating with vibration energy of a target biological material.

Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a sacrificial spacer over a substrate and forming a select gate along a side of the sacrificial spacer. An inter-gate dielectric is formed over the select gate and the sacrificial spacer. A memory gate layer is formed over the inter-gate dielectric and the sacrificial spacer. The memory gate layer is laterally separated from the sacrificial spacer by the select gate. The memory gate layer is etched to define a memory gate having a topmost point below a top of the sacrificial spacer.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A image sensor includes a first integrated circuit layer including pixel sensors that are grouped based on position into pixel sensor groups, a second integrated circuit layer in electrical communication with the first integrated circuit layer, the second integrated circuit layer including image processing circuitry groups that are configured to each receive pixel information from a corresponding pixel sensor group, the image processing circuitry groups further configured to perform image processing operations on the pixel information to provide processed pixel information during operation of the image sensor, a third integrated circuit layer in electrical communication with the second integrated circuit layer, and the third integrated circuit layer including neural network circuitry groups that are configured to each receive the processed pixel information from a corresponding image processing circuitry group and perform analysis for object detection on the processed pixel information during operation of the

Abstract: An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes preparing a lead frame. The lead frame includes a first lead including a pad and a first terminal. The pad includes a pad main surface and a pad back surface that face opposite sides to each other in a first direction. The first terminal extends from the pad along a second direction that is perpendicular to the first direction.

Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

Abstract: A method of producing optoelectronic semiconductor components including providing a primary light source having a carrier and a semiconductor layer sequence mounted thereon that generates primary light (B), wherein the semiconductor layer sequence is structured into a plurality of pixels that can be driven electrically independently of each other, and the carrier includes a plurality of control units that drive the pixels, providing at least one conversion unit adapted to convert the primary light (B) into at least one secondary light (G, R), wherein the conversion unit is grown continuously from at least one semiconductor material, structuring the conversion unit, wherein portions of the semiconductor material are removed in accordance with the pixels, and applying the conversion unit to the semiconductor layer sequence so that the remaining semiconductor material is uniquely assigned to a portion of the pixels.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.