Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.

Abstract: A display device including a display area and a non-display area, a substrate including a through hole in the display area, an element layer including an anode disposed on the substrate, a light emitting layer disposed on the anode, and a cathode disposed on the light emitting layer, and a thin-film encapsulation layer including a first inorganic layer disposed on the element layer, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer, in which the first inorganic layer includes a plurality of first refractors having a first inclination angle.

Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

Abstract: A display device including a substrate that includes a circuit layer; an insulating layer on the substrate; a pixel defining layer on the insulating layer, the pixel defining layer having an opening exposing a region of a top surface of the insulating layer; a light blocking layer covering a top surface and a side surface of the pixel defining layer; and an organic electroluminescent element in the opening, wherein the organic electroluminescent element includes a first electrode on the region of the top surface of the insulating layer exposed through the opening; at least one organic layer on the first electrode; and a second electrode on the at least one organic layer.

Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

Abstract: The present disclosure provides an array substrate which comprises a plurality of sub-pixels distributed in an array arrangement, wherein data lines and power supply signal lines are disposed between two adjacent columns of the sub-pixels; wherein the data lines and the power supply signal lines are prepared respectively on different film layer surfaces, and the data lines and the power supply signal lines at least partially overlap. The present disclosure further provides an OLED display device which comprises the array substrate. The array substrate of the present disclosure has a higher aperture ratio.

Abstract: The energy density of capacitors can be increased by using a material with differential negative capacitance (NC), which was recently observed in FE materials. Described is a more general pathway towards improved electrostatic energy storage densities by engineering the capacitance non-linearity of electrostatic devices. The disadvantages of regular polarizable materials are overcome by using the NC effect, which ideally has no hysteresis losses, leading to a theoretical efficiency of 100%. By storing the energy mostly in an amorphous DE layer, the break-down field strength is much higher compared to pure FE or AFE storage capacitors. In addition, leakage current losses can be reduced by improving the morphology of the insulating materials used.

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: A radiation emitting component and a method for producing a radiation emitting component are disclosed. In an embodiment a radiation emitting component includes a radiation emitting semiconductor chip having an active zone configured to generate electromagnetic radiation of a first wavelength range, a reflector having side walls and a bottom surface and a conversion layer comprising a first phosphor configured to convert the electromagnetic radiation of the first wavelength range into electromagnetic radiation of a second wavelength range, wherein the conversion layer is located at the side walls of the reflector, wherein the conversion layer has a cross-sectional area, which decreases from the bottom surface of the reflector to a radiation exit surface of the component, and wherein the reflector is filled with a conversion element comprising a second phosphor configured to convert electromagnetic radiation of the first wavelength range into electromagnetic radiation of a third wavelength range.

Abstract: An image sensor includes a semiconductor substrate of first conductivity type having first and second surfaces and including pixel regions, photoelectric conversion regions of second conductivity type respectively provided in the pixel regions, and a pixel isolation structure disposed in the semiconductor substrate to define the pixel regions and surrounding each of the photoelectric conversion regions. The pixel isolation structure includes a semiconductor pattern extending from the first surface to the second surface of the semiconductor substrate, a sidewall insulating pattern between a sidewall of the semiconductor pattern and the semiconductor substrate, and a dopant region in at least a portion of the semiconductor pattern.

Abstract: A semiconductor memory device includes a substrate, a plurality of landing pads, a first conducting layer, a plurality of first capacitors, a plurality of second capacitors, a second conducting layer and a plurality of third capacitors. The substrate has an active area, and the active area has a first area, a second area and a third area. The third area surrounds the first area. The second area surrounds the first area and the third area. The landing pads are disposed on the first area. The first conducting layer is disposed on the second area. The first capacitors are disposed on the landing pads respectively. The second capacitors are disposed on the first conducting layer. The second conducting layer is disposed on the second capacitors. The third capacitors are disposed in the third area. The second conducting layer is not electrically connected to the third capacitors.

Abstract: A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

Abstract: A micro LED display device including a display substrate, a plurality of conductive pad pairs and a plurality of micro light emitting elements is provided. The display substrate has a first arranging area, a splicing area connected to the first arranging area, and a second arranging area connected to the splicing area, wherein the splicing area is located between the first arranging area and the second arranging area. The conductive pad pairs are disposed on the display substrate in an array with the same pitch. The micro light emitting elements are disposed on the display substrate and are electrically bonded to the conductive pad pairs. A manufacturing method of the micro LED display device is also provided.

Abstract: A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.

Abstract: Spin-orbit-torque (SOT) lines are provided near free regions in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT lines injects spin current into the free regions such that spin torque is applied to the free regions. The spin torque generated from a SOT switching line can be used to switching the free region or to act as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction, in order to improve the reliability, endurance, or both of the magnetoresistive device. Further, one or more additional layers or regions may improve the SOT switching efficiency and the thermal stability of magnetoresistive devices including SOT lines.

Abstract: An LED module includes a substrate having a high thermal conductivity and at least one LED die mounted on the substrate. A wavelength conversion material, such as phosphor or quantum dots in a binder, has a very low thermal conductivity and is formed to have a relatively high volume and low concentration over the LED die so that the phosphor or quantum dots conduct little heat from the LED die. A transparent top plate, having a high thermal conductivity, is positioned over the wavelength conversion material, and a hermetic seal is formed between the top plate and the substrate surrounding the wavelength conversion material. The LED die is located in a cavity in either the substrate or the top plate. In this way, the temperature of the wavelength conversion material is kept well below the temperature of the LED die. The sealing is done in a wafer level process.

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

Abstract: A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure.