Abstract: To provide a highly reliable semiconductor device that is suitable for miniaturization and an increase in density. The semiconductor device includes a first insulator over a substrate, a transistor including an oxide semiconductor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The first insulator and the third insulator have a barrier property with respect to oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor is enclosed with the first insulator and the third insulator that are in contact with each other in an edge of a region where the transistor is positioned.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.

Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

Abstract: A display apparatus includes a base substrate, a thin film transistor disposed on the base substrate and including an active pattern, a gate electrode, a source electrode, and a drain electrode, an inorganic insulating layer disposed between the active pattern and the gate electrode, a first organic insulating layer disposed on the thin film transistor, a second organic insulating layer disposed on the first organic insulating layer, and an insulating layer disposed between the first organic insulating layer and the second organic insulating layer and in direct contact with the first organic insulating layer and the second organic insulating layer.

Abstract: A semiconductor device package is provided, including a semiconductor device, a molding material, and a conductive slot. The molding material surrounds the semiconductor device. The conductive slot is positioned over the molding material and having an opening and at least two channels connecting the opening to the edges of the conductive slot.

Abstract: A semiconductor structure includes vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches. Laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures are located within a respective one of the line trenches. Memory films are located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure including a pair of lateral semiconductor channels that laterally connect the source pillar structure and the drain pillar structure. The memory films may include a charge storage layer or a ferroelectric material layer.

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.

Abstract: The present invention relates to a package-before-etch three-dimensional package structure electrically connected by plated copper pillars and a process thereof. The process comprises the following steps: taking a metal carrier; preplating a surface of the metal carrier with a copper layer; forming an outer metal pin by means of electroplating; performing plastic packaging with epoxy resin; forming a metal circuit layer by means of electroplating; forming a conductive metal pillar by means of electroplating; surface-mounting a chip; performing plastic packaging; surface-mounting a passive device; performing plastic packaging; etching and windowing the carrier; forming an anti-oxidant metal layer by means of electroplating; and performing cutting to obtain a finished product. The integration level and the reliability can be improved.

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.

Abstract: Provided is a semiconductor memory device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating layer provided between the semiconductor layer and at least one of the gate electrode layers, and the gate insulating layer including a first region containing a first oxide including at least one of a hafnium oxide and a zirconium oxide, in which a first length of the at least one of the gate electrode layers in the first direction is larger than a second length of the first region in the first direction.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell source structure; a first stack structure disposed on the cell source structure; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions. A level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure.

Abstract: There is provided a semiconductor device including: a first semiconductor element including a first gate electrode, a first source electrode, and a first drain electrode; a second semiconductor element including a second gate electrode, a second source electrode, and a second drain electrode; a gate lead, a source lead, a first drain lead, and a second drain lead; and a resin part, wherein the first gate electrode and the first source electrode, and the first drain electrode are provided on opposite sides to each other in a first direction, wherein the second gate electrode and the second source electrode, and the second drain electrode are provided on opposite sides to each other in the first direction, wherein the first gate electrode and the second gate electrode are opposed to the first source electrode and the second source electrode, respectively, in the first direction.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.