Abstract: The present disclosure provides a semiconductor structure, including: a first layer including a logic device; and a second layer over the first layer, including a first type memory device, a though silicon via (TSV) electrically connecting the logic device and the first type memory device. A method of forming semiconductor structure is also disclosed.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a gate electrode, a source electrode, a drain electrode, a conductive member, a gate terminal, and a first circuit. The semiconductor member includes a first semiconductor layer including a first partial region and including Alx1Ga1?x1N (0?x1?1), and a second semiconductor layer including Alx2Ga1?x2N (0<x2?1 and x1<x2). The first partial region is between the gate electrode and at least a portion of the conductive member in a first direction. The gate terminal is electrically connected to the gate electrode. The first circuit is configured to apply a first voltage to the conductive member based on a gate voltage applied to the gate terminal. The first voltage has a reverse polarity of a polarity of the gate voltage.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a source/drain structure, a metal gate structure, a ferroelectric layer, a spacer and a metal layer. The source/drain structure is disposed over the substrate. The metal gate structure is disposed over the substrate and between the source/drain structure. The ferroelectric layer is disposed over the metal gate structure and the source/drain structure. The spacer is disposed over the ferroelectric layer. The metal layer is disposed over the ferroelectric layer and surrounded by the spacer. A method for manufacturing a semiconductor structure is also provided.

Abstract: A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

Abstract: The image sensing device includes a pixel array including a plurality of unit pixels is arranged in rows and columns. Each of the plurality of unit pixels includes a photoelectric conversion element to generate charge carriers by converting light incident upon the photoelectric conversion element, a plurality of floating diffusion regions spaced apart from the photoelectric conversion element to hold the charge carriers, a plurality of circulation gates located at sides of the photoelectric conversion element in each of a first direction and a second direction perpendicular to the first direction, configured to create an electric field in different regions of the photoelectric conversion element based on circulation control signals, and configured to induce movement of the charge carriers, and a plurality of transfer gates located between the circulation gates, and configured to transfer the charge carriers generated by the photoelectric conversion element to a corresponding floating diffusion region.

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, a ferroelectric film, a first seed layer and a control gate electrode. The semiconductor substrate includes a source region and a drain region which are formed on a main surface of the semiconductor substrate. The insulating film is formed on the main surface of the semiconductor substrate such that the insulating film is positioned between the source region and the drain region in a plan view. The ferroelectric film is formed on the insulating film and includes hafnium and oxygen. The first seed layer is formed on the ferroelectric film. The control gate electrode is formed on the ferroelectric film. A material of the first seed layer includes at least one material of the ferroelectric film and at least one material of the first conductive film.

Abstract: An image sensor and an electronic device are disclosed. At least one pixel in the image sensor includes a photodiode, a floating diffusion region and a transfer transistor located between the photodiode and the floating diffusion region. The photodiode includes a carrier-accumulation region, and a gate of the transfer transistor extends up to the carrier-accumulation region. The gate extends away from the floating diffusion region and overlaps over half of a width of the carrier-accumulation region. Since carriers move at a higher speed in a fast transfer channel in the semiconductor substrate around such a gate, increasing the length of the transfer transistor's gate extending away from the floating diffusion region and overlapping range with the carrier-accumulation region can facilitate fast movement of carriers from the carrier-accumulation region through such fast transfer channels to the floating diffusion region, thereby improving overall carrier transfer efficiency and optimizing performance thereof.

Abstract: The present invention provides a light-emitting device including a substrate, a first EL element, and a second EL element, the first EL element and the second EL element each including a lower electrode, an organic compound layer including a light-emitting layer, an upper electrode, and a color filter in this order from the substrate, and an insulating layer that covers an end portion of the lower electrode. A first color filter of the first EL element and a second color filter of the second EL element overlap each other when viewed in plan in an overlapping region, and an inclined portion closest to the first EL element among inclined portions of the insulating layer of the second EL element and the overlapping region overlap each other when viewed in plan.

Abstract: Provided are a method for manufacturing wavelength conversion members that enables manufacturing of wavelength conversion members having a high light extraction efficiency and suppression of material loss, a wavelength conversion member obtained by the method, and a light-emitting device.

Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

Abstract: A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

Abstract: The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device.

Abstract: A first amorphous film including hafnium, oxygen and a first element is formed, and a plurality of grains including a second element which differs from any of hafnium, oxygen and the first element is formed on the first amorphous film. An insulating film including a third element that differs from any of hafnium and the second element is formed over the plurality of grains and the first amorphous film, thereby forming a plurality of grains including the second element and the third element. A second amorphous film including the same materials as those of the first amorphous film is formed on the plurality of grains and the first amorphous film. By performing heat treatment, the first amorphous film and the second amorphous film are crystallized to form a first ferroelectric film which is an orthorhombic and a second ferroelectric film which is an orthorhombic, respectively.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a ferroelectric layer disposed between the first electrode and the second electrode, and a recess between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.

Abstract: A display apparatus including: a base substrate; a first active pattern disposed on the base substrate, a first insulating layer disposed on the first active pattern; a first gate electrode disposed on the first insulating layer; a second insulating layer disposed on the first gate electrode; a ring dummy pattern disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer; and a first drain electrode disposed on the third insulating layer, and electrically connected to the first active pattern through a contact hole which is formed through the third insulating layer, the second insulating layer and the first insulating layer, wherein the first drain electrode is disposed in an opening of the ring dummy pattern.

Abstract: A FET device has a substrate, a plurality of repetitive source stripes, a first layout of drain stripe having a first drift region and a first drain region, a second layout of drain stripe having a second drift region and a second drain region, a first drain contactor contacted with the first drain region and connected to a drain terminal, a second drain contactor contacted with the second drain region and connected to a first gate terminal, a source contactor contacted with a source region in each of the plurality of repetitive source stripes and connected to a source terminal, a first gate region positioned between the source region and the first drain region and connected to the first gate terminal, and a second gate region positioned between the source region and the second drain region and connected to a second gate terminal.