Patents Examined by Matthew Gordon
  • Electrostatic discharge protection structure
    Patent number: 9449960
    Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 20, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang
  • Lateral type photodiode, image sensor including the same, and method of manufacturing the photodiode and the image sensor
    Patent number: 9450122
    Abstract: Example embodiments relate to a lateral type photodiode including a substrate, an insulation mask layer formed on the substrate, and a first type semiconductor layer, an active layer, and a second type semiconductor layer that contact a surface of the insulation mask layer and that are sequentially disposed in a direction substantially parallel to the surface of the insulation mask layer. The insulation mask layer includes a through hole, and the first type semiconductor layer, the active layer, and the second type semiconductor layer are sequentially formed from the through hole by using a lateral overgrowth method.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihoon Ahn, Yongwoo Jeon, Jungwoo Kim, Haeseok Park, Seungeon Ahn, Seunghyup Lee, Myounghoon Jung, Hyuksoon Choi
  • Photodiode of high quantum efficiency
    Patent number: 9450000
    Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: September 20, 2016
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Michel Marty, Sebastien Jouan, Laurent Frey, Salim Boutami
  • Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die
    Patent number: 9449932
    Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Trasporto, Linda Pei Ee Chua, Reza A. Pagaila
  • MEMS microphone module and manufacturing process thereof
    Patent number: 9445212
    Abstract: A micro-electro-mechanical system (MEMS) microphone module and a manufacturing process thereof are described. A thickness of a transparent temporary cover plate temporarily disposed in a conventional plastic package structure is adjusted. After a mold for a plastic protector is formed, an UV ray is utilized to irradiate the mold to reduce adherence on the temporary cover plate and a back surface of the MEMS acoustic wave sensing chip. Then, the temporary cover plate is removed, and the left space left is the main source for the back-volume of the MEMS microphone. Finally, a tag is covered on the plastic protector, so as to define the whole back-volume and form a closed back-volume. In the above-mentioned process, the size of the back-volume is the same as an area of the whole MEMS microphone chip. In addition, the back-volume can be defined.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: September 13, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Lung-Tai Chen, Chun-Hsun Chu, Wood-Hi Cheng
  • Semiconductor module including plate-shaped insulating members having different thickness
    Patent number: 9443784
    Abstract: A power semiconductor chip and a low-power portion that has power consumption lower than that of the power semiconductor chip are located on a predetermined surface side of a heat sink having conductivity. A first plate-shaped insulating member extends between the power semiconductor chip and the heat sink. A second plate-shaped insulating member extends between the low-power portion and the heat sink. A portion, which faces the low-power portion, of the second plate-shaped insulating member is thicker than a portion, which faces the power semiconductor chip, of the first plate-shaped insulating member.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 13, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kenji Hatori
  • Semiconductor device and method of manufacturing the same
    Patent number: 9443893
    Abstract: A solid-state image sensing element including a transistor with stable electrical characteristics (e.g., significantly low off-state current) is provided. Two different element layers (an element layer including an oxide semiconductor layer and an element layer including a photodiode) are stacked over a semiconductor substrate provided with a driver circuit such as an amplifier circuit, so that the area occupied by a photodiode is secured. A transistor including an oxide semiconductor layer in a channel formation region is used as a transistor electrically connected to the photodiode, which leads to lower power consumption of a semiconductor device.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: September 13, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Method and apparatus for measuring phosphorylation kinetics on large arrays
    Patent number: 9442111
    Abstract: The disclosure provides for methods and apparatuses relating to technology for monitoring chemical and/or biological reactions. Some methods provided herein relate to utilization of NAPPA technology to create large protein arrays suitable for use in combination with various ISFET arrays to enable massive parallel assays of kinase activity and inhibition. Some devices provided herein relate to CMOS chips which utilize the NAPPA array technology to build protein inventories of interest upon an ISFET architecture. Further devices provided herein are capable, inter alia, of processing the arrays created by the combination of NAPPA technology and ISFET architecture.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 13, 2016
    Assignee: ARIZONA BOARD OF REGENTS
    Inventors: Stuart Lindsay, Joshua Labaer
  • Method for manufacturing semiconductor device having grooved surface
    Patent number: 9437719
    Abstract: A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor device includes: forming an oxide film 62 on a surface 12b of a semiconductor substrate 12 by bringing the surface 12b into contact with ammonia-hydrogen peroxide water mixture; forming a groove 60 on the surface 12b by irradiating light to heat the surface 12b covered with the oxide film 62; removing the oxide film 62 to expose the surface 12b; and forming an electrode 16 on the exposed surface 12b.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 6, 2016
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shuhei Oki, Masaru Senoo
  • Method and apparatus for cooling wafer in ion implantation process
    Patent number: 9437433
    Abstract: Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: September 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Yuan Ho, Jung-Wei Lee, Ming-Te Chen
  • Dual channel FinFET CMOS device with common strain-relaxed buffer and method for manufacturing thereof
    Patent number: 9437681
    Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 6, 2016
    Assignees: IMEC VZW, Samsung Electronics Co. Ltd.
    Inventors: Seung Hun Lee, Geert Eneman
  • Light emitting device including resin package having differently curved parts
    Patent number: 9425235
    Abstract: A light emitting device, having: a first light emitting element and a second light emitting element; and a resin package equipped with an opening having a reflective wall that widens toward the upper face, the opening comprises at least first and second curved parts having different radiuses at the resin package upper face, and the radius of the first curved part disposed near the first light emitting element is greater than the radius of the second curved part disposed near the second light emitting element.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: August 23, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Toshimasa Takao, Takeo Kurimoto
  • Method for forming semiconductor device including spacers having different dimensions
    Patent number: 9425274
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Image sensor with reduced optical path
    Patent number: 9425228
    Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler gird portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler gird portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shyh-Fann Ting, Ching-Chun Wang, Wei Chuang Wu, Yu-Jen Wang, Chun-Ming Su, Jhy-Jyi Sze, Chen-Jong Wang
  • Three-dimensional semiconductor memory device having sidewall and interlayer molds
    Patent number: 9418911
    Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Joo Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Woojin Cho
  • Method for forming package-on-package structure
    Patent number: 9412661
    Abstract: A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second top package on the first side of the wafer. The method further comprises depositing an encapsulation layer over the first side of the wafer, wherein the first top package and the second top package are embedded in the encapsulation layer, applying a thinning process to a second side of the wafer, sawing the wafer into a plurality of chip packages and attaching the chip package to a substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Ming-Kai Liu, Kai-Chiang Wu, Ching-Feng Yang
  • Reduced off current switching transistor in an organic light-emitting diode display device
    Patent number: 9412303
    Abstract: An active matrix organic light emitting diode (OLED) display device includes an array of pixels, each pixel including an OLED, a driving transistor (DT) coupled to drive current through the OLED, a storage capacitor, and a scanning transistor (ST) coupled to control charge on the storage capacitor corresponding to a data voltage for said pixel. The display device also includes a timing controller configured to control the ST of each pixel to update the charge stored on the storage capacitor of each pixel at a frame rate including at least one frequency within a range of 1-10 Hertz (Hz).
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 9, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Junghyeon Kim, Hyungjin Bang
  • Organic electroluminescent element and electronic device
    Patent number: 9406897
    Abstract: An organic electroluminescent element includes a layer having a shallower LUMO and a higher T1 than those of the first light-emitting layer on the anode side of the first light-emitting layer, and a layer which satisfies at least one of a deeper LUMO and includes a lower T1 than those of the second light-emitting layer on the anode side of the second light-emitting layer, and provides the organic electroluminescent element capable of suppressing the lowering of display quality.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 2, 2016
    Assignee: KONICA MINOLTA, INC.
    Inventors: Ken Okamoto, Rieko Takahashi, Kenji Arai
  • Methods of packaging semiconductor devices and structures thereof
    Patent number: 9406581
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Post-mold for semiconductor package having exposed traces
    Patent number: 9397031
    Abstract: Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple semiconductor packages into a molding device, adding a molding material on a surface of the leadframe, molding the molding material, such that the molding material covers the entire surface of the semiconductor packages except conducting terminals, and singulating the semiconductor packages from the leadframe after molding the molding material.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 19, 2016
    Assignee: UTAC THAI LIMITED
    Inventor: Saravuth Sirinorakul