Patents Examined by Matthew L. Reames
  • Patent number: 12289885
    Abstract: Three-dimensional (3D) NAND memory structures and methods to manufacture 3D NAND memory structures are disclosed. A method includes forming a stack of layers that includes a first sub-stack for a transistor structure and a second sub-stack for a memory structure positioned on the first sub-stack. The second sub-stack includes at least one layer of conductive material and at least one layer of non-conductive material. The first sub-stack and the second sub-stack are separated by at least one non-conductive layer. The method includes forming a channel opening in the stack of layers, forming a gate dielectric in the channel opening, and providing a channel structure within the channel opening. The channel structure includes a semiconductive-behaving material and aligned with the transistor structure. The method includes providing a charge trap layer within the channel opening and aligned with the memory structure.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: April 29, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 12266748
    Abstract: A display device includes a substrate including a display area and a non-display area, a pixel circuit portion disposed on the substrate and including a transistor that drives a pixel, and a display element portion disposed on the pixel circuit portion and including a pixel electrode electrically connected to an electrode of the transistor through a bridge pattern. The pixel circuit portion includes a first capping layer disposed between the bridge pattern and the pixel electrode, and the pixel electrode and the bridge pattern are multiple metal layers including a same material.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 1, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Su Jin Lee, Jae Yong Jang, Jin Woo Choi, Bon Yong Koo
  • Patent number: 12265886
    Abstract: The present disclosure describes non-classical (e.g., quantum) computing systems and methods that utilize dopant molecules contained in host materials as qubits.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: April 1, 2025
    Assignee: NVision Imaging Technologies GmbH
    Inventors: Ilai Schwartz, Matthias Pfender, Tobias Schaub, Philipp Neumann
  • Patent number: 12266609
    Abstract: A semiconductor package includes a first semiconductor chip, which includes a first semiconductor substrate and a first bonding layer on the first semiconductor substrate. A second semiconductor chip includes a second semiconductor substrate, a second bonding layer bonded to the first bonding layer, and a chip-through-via which penetrates the second semiconductor substrate and is connected to the second bonding layer. A passivation film extends along an upper side of the second semiconductor chip and does not extend along side-faces of the second semiconductor chip. The chip-through-via penetrates the passivation film. A multiple-gap-fill film extends along the upper side of the first semiconductor chip, the side faces of the second semiconductor chip, and the side faces of the passivation film. The multiple-gap-fill films includes an inorganic filling film and an organic filling film which are sequentially stacked on the first semiconductor chip.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 1, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung Jun Jeon, Kwang Jin Moon, Son-Kwan Hwang
  • Patent number: 12268033
    Abstract: There is disclosed an ultraviolet (UV) photo sensing element comprising a GaN substrate and a Ta2O5 thin film layer, forming a GaN (gallium-nitride) and Ta2O5 (tantalum pentoxide) based heterojunction wherein the formed heterojunction receives and converts UV light into electrical signals/in the photovoltaic mode (at 0 V) or in a self-driven mode. Also disclosed is a method of fabrication of an ultraviolet (UV) photodetector (PD) device, the method comprising growing silicon-doped n-type GaN epitaxial layers on a stack of un-doped GaN/sapphire samples, cleaning the GaN samples, pelletizing and depositing tantalum pentoxide (Ta2O5) powder on the n-type GaN samples, forming Ta2O5/GaN stacks, post-annealing the formed Ta2O5/GaN stacks; and depositing high purity Au on the Ta2O5/GaN stacks. The photodetector (PD) device is a heterojunction ultraviolet (UV) photodetector (PD) device.
    Type: Grant
    Filed: April 19, 2024
    Date of Patent: April 1, 2025
    Assignee: UNITED ARAB EMIRATES UNIVERSITY
    Inventors: Sambasivam Sangaraju, Nanda Kumar Reddy Nallabala
  • Patent number: 12261257
    Abstract: A colour micro-LED display apparatus comprises an array of reflective optical elements and an array of micro-LED pixels with a uniform emission colour across the array arranged between the army of reflective optical elements and an output substrate. Light from the micro-LEDs is directed into the reflective optical elements and is incident on scattering regions in the apparatus. Colour converted scattered light is transmitted by the output substrate. A thin and efficient display apparatus may be provided with high spatial and angular colour uniformity and long lifetime.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: March 25, 2025
    Assignee: RealD Spark, LLC
    Inventors: Graham J. Woodgate, Jonathan Harrold, Michael G. Robinson
  • Patent number: 12253483
    Abstract: The various embodiments described herein include methods for manufacturing superconductor devices. A method for manufacturing superconductors may include: (i) generating spectra data from a first superconductor device; (iii) identifying a first peak ratio between a first phase peak and a second phase peak in the spectra data; (iv) generating additional spectra data from a second superconductor device; (v) identifying a second peak ratio of the additional spectra data from the second superconductor device; (vi) adjusting a manufacturing parameter based on the first peak ratio and the second peak ratio; and (vii) manufacturing a third superconductor device based on the adjusted manufacturing parameter.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: March 18, 2025
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Chia-Jung Chung
  • Patent number: 12243971
    Abstract: A display device according to some embodiments includes a substrate, a first power line extending in a first direction on the substrate, and configured to transmit a first alignment signal or a first driving voltage, a second power line extending in the first direction on the substrate, and configured to transmit a second alignment signal or a second driving voltage, a first electrode extending in a second direction that is substantially perpendicular to the first direction, configured to receive the first alignment signal or the first driving voltage, and electrically connected to the first power line, a second electrode spaced apart from the first electrode, extending in the second direction, configured to receive the second alignment signal or the second driving voltage, and electrically connected to the second power line, and a light emitting element between the first electrode and the second electrode.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: March 4, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki Hyun Pyo, Jin Seon Kwak, Kyung Bae Kim, Yeon Kyung Kim, Ji Hye Lee
  • Patent number: 12245461
    Abstract: A display apparatus includes: a substrate including a main display area, a component area, and a peripheral area; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being disposed on the main display area; an auxiliary display element disposed on the component area; an auxiliary pixel circuit arranged on the peripheral area; and a connection line connecting the auxiliary display element to the auxiliary pixel circuit. The auxiliary display element includes an auxiliary pixel electrode that is at least partially round. The auxiliary pixel electrode has an asymmetrical shape with a contact portion at one side thereof. The contact portion is connected to the connection line.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 4, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sungjin Hong, Chungsock Choi, Juhoon Kang, Joohee Jeon, Sunyoung Jung
  • Patent number: 12239027
    Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: February 25, 2025
    Assignee: Google LLC
    Inventors: Brian James Burkett, Ofer Naaman, Anthony Edward Megrant, Theodore Charles White
  • Patent number: 12230636
    Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 12225831
    Abstract: The present disclosure provides a superconducting qubit. The superconducting qubit includes: a Josephson junction and a non-Josephson junction area, wherein the non-Josephson junction area includes a first layer of superconducting material, the first layer of superconducting material being superconducting material deposited on the non-Josephson junction area before ion milling on the Josephson junction and the non-Josephson junction area during preparation of the superconducting qubit.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: February 11, 2025
    Assignee: Alibaba Group Holding Limited
    Inventor: Hao Deng
  • Patent number: 12216381
    Abstract: A method of generating a photon with multiple dimensions includes a step of generating a first photon encoded with quantum information in each of two or more frequency bins and at least one time bin. The method further includes performing a frequency dependent time operation to entangle (i.e. make non-separable) the frequency bins and the time bins in the photon.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: February 4, 2025
    Assignee: Purdue Research Foundation
    Inventors: Andrew Weiner, Poolad Imany
  • Patent number: 12200972
    Abstract: A display apparatus includes: a substrate including a main display area, a component area, and a peripheral area; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being disposed on the main display area; an auxiliary display element disposed on the component area; an auxiliary pixel circuit arranged on the peripheral area; and a connection line connecting the auxiliary display element to the auxiliary pixel circuit. The auxiliary display element includes an auxiliary pixel electrode that is at least partially round. The auxiliary pixel electrode has an asymmetrical shape with a contact portion at one side thereof. The contact portion is connected to the connection line.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sungjin Hong, Chungsock Choi, Juhoon Kang, Joohee Jeon, Sunyoung Jung
  • Patent number: 12196893
    Abstract: An X-ray device including a sensing panel and a scintillator layer is provided. The sensing panel includes a substrate and a first pixel. The first pixel is disposed on the substrate and includes a first light sensing component and a first switch component. The first switch component is disposed on the first light sensing component. The scintillator layer is disposed on the sensing panel, and the first switch component is disposed between the scintillator layer and the first light sensing component.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 14, 2025
    Assignee: InnoCare Optoelectronics Corporation
    Inventor: Zhi-Hong Wang
  • Patent number: 12187941
    Abstract: A quantum dot having a core including a first semiconductor nanocrystal including zinc, selenium, and tellurium, and a semiconductor nanocrystal shell disposed on the surface of the core, the shell including zinc, selenium, and sulfur. The quantum dot is configured to emit green light, the quantum dot does not include cadmium, and the quantum dot has a mole ratio Te:Se of tellurium relative to selenium of greater than about 0.05 and less than or equal to about 0.5:1. A method of producing the quantum dot and an electronic device including the same.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: January 7, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuho Won, Yong Wook Kim, Eun Joo Jang, Hyo Sook Jang
  • Patent number: 12185643
    Abstract: A superconducting device includes a substrate, a metal oxide or metal oxynitride seed layer on the substrate, and a metal nitride superconductive layer disposed directly on the seed layer. The seed layer is an oxide or oxynitride of a first metal, and the superconductive layer is a nitride of a different second metal.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: December 31, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Zihao Yang, Mingwei Zhu, Shriram Mangipudi, Mohammad Kamruzzaman Chowdhury, Shane Lavan, Zhebo Chen, Yong Cao, Nag B. Patibandla
  • Patent number: 12183625
    Abstract: A method for preparing semiconductor on insulator structures comprises transferring a thin layer of silicon from a donor substrate onto a handle substrate.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: December 31, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gaurab Samanta, Salvador Zepeda
  • Patent number: 12178143
    Abstract: A superconducting complex quantum computing circuit includes a circuit substrate in which a wiring pattern of a circuit element including quantum bits and measurement electrodes, and ground patterns are formed, and through-electrodes connecting the ground pattern formed on a first surface of the substrate surface and the ground pattern formed on a second surface; a first ground electrode including a first contact portion in contact with the ground patterns, and a first non-contact portion having a shape corresponding to a shape of the wiring pattern; a second ground electrode including a second contact portion in contact with the ground pattern; a control signal line provided with a contact spring pin at a tip; and a pressing member that presses the first ground electrode against the first surface of the circuit substrate or presses the second ground electrode against the second surface of the circuit substrate.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 24, 2024
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yasunobu Nakamura, Yutaka Tabuchi, Shuhei Tamate
  • Patent number: 12171147
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 17, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra