Patents Examined by Matthew L. Reames
  • Patent number: 11990557
    Abstract: There is provided an optical sensor package including a substrate, a base layer, an optical detection region, a light source and a light blocking wall. The base layer is arranged on the substrate. The light detection region and the light source are arranged on the base layer. The light blocking wall is arranged on the base layer, and located between the light detection region and the light source to block light directly propagating from the light source to the light detection region.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 21, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chi-Chih Shen, Kuo-Hsiung Li, Shang-Feng Hsieh, Jui-Cheng Chuang, Yi-Chang Chang
  • Patent number: 11990489
    Abstract: A plurality of photoelectric converters is formed on a semiconductor substrate and performs photoelectric conversion according to incident light. A light path portion includes a transparent film through which the incident light is transmitted, a light-blocking wall for each of the plurality of photoelectric converters, the light-blocking wall partitioning the transparent film in a direction perpendicular to the semiconductor substrate, and blocking light, and a light-blocking film at an end of the light-blocking wall, the end being opposite to an end of the light-blocking wall that is closer to the semiconductor substrate, the light-blocking film having a film shape parallel to the semiconductor substrate, and including, for each of the plurality of photoelectric converters, an opening through which the incident light is transmitted.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 21, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro Noudo, Takuji Matsumoto, Yuji Iseri, Taizo Oishi
  • Patent number: 11978626
    Abstract: In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 7, 2024
    Assignee: SK hynix Inc.
    Inventors: Won Tae Koo, Mir Im
  • Patent number: 11972990
    Abstract: A unit includes a wiring board having a first face having a mounting portion on which an electronic device is mounted, a second face opposite to the first face, and end faces continuous with the first face and the second face, a resin member provided to cover the end faces and to have protrusions protruding upward from the end faces to face each other across a space above the mounting portion, and an insulating film covering the second face, wherein at least a part of an edge of the insulating film is provided away from an end of the second face on the end face side.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 30, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Nozu, Yu Aoki, Hirotaka Sekiguchi, Koji Sato, Koji Tsuduki
  • Patent number: 11968903
    Abstract: Provided are a piezoelectric element for a speaker and a method of manufacturing the same. The piezoelectric element for a speaker includes a plurality of piezoelectric ceramic layers stacked on one another in a thickness direction, and a plurality of electrodes provided to be connected to middle portions of sides of the plurality of piezoelectric ceramic layers along external walls of the plurality of stacked piezoelectric ceramic layers, wherein middle portions of some sides from among a plurality of sides of each of the plurality of piezoelectric ceramic layers are etched, and wherein the plurality of piezoelectric ceramic layers are stacked on one another in the thickness direction not to overlap non-etched sides from among the plurality of sides.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jisun Kim, Taeyoung Kim, Joungkook Seo, Sanghoon Choi
  • Patent number: 11950516
    Abstract: The present disclosure relates to a method for manufacturing of specially designed substrates for growth of nanostructures and patterned growth on said nanostructures. The present disclosure further relates to nanostructures, in particular hybrid semiconductor nanostructures with patterned growth of superconducting material for use in quantum devices. The presently disclosed method can be utilized for in-situ manufacturing of quantum devices that have not been contaminated by ex-situ processes.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 2, 2024
    Assignee: University of Copenhagen
    Inventors: Thomas Sand Jespersen, Jesper Nygård, Damon Carrad, Martin Bjergfelt
  • Patent number: 11948985
    Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: April 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
  • Patent number: 11948929
    Abstract: In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Nakaki
  • Patent number: 11934916
    Abstract: An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: March 19, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun Li, Shih-Yuan Chen, Yao-Chun Chang, Ian Huang, Chiung-Yu Chen
  • Patent number: 11935981
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
  • Patent number: 11937521
    Abstract: A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: March 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Choonghyun Lee
  • Patent number: 11922276
    Abstract: A device includes: a substrate; a superconducting quantum interference device (SQUID) including a superconductor trace arranged on an upper surface of the substrate and having at least one Josephson junction interrupting a path of the superconductor trace, in which the superconductor trace includes a first superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature; and a dielectric capping layer on an upper surface of the SQUID, in which the dielectric capping layer covers a majority of the superconductor trace of the SQUID, and the capping layer includes an opening through which a first region of the SQUID is exposed, the first region of the SQUID including a first Josephson junction.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 5, 2024
    Assignee: Google LLC
    Inventor: Rami Barends
  • Patent number: 11925122
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 5, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 11923466
    Abstract: A photodetector with an integrated reflective grating structure includes a substrate, an active layer disposed on the substrate, and a grating structure disposed between the substrate and the active layer. A first doped region is formed on the substrate at a location near the grating structure. A second doped region is formed on a surface of the active layer away from the grating structure. The doping type of the second doped region is different from that of the first doped region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 5, 2024
    Assignee: INNOLIGHT TECHNOLOGY (SUZHOU) LTD.
    Inventors: Chih-Kuo Tseng, Guoliang Chen, Xiaoyao Li, Yuzhou Sun, Yue Xiao
  • Patent number: 11923271
    Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Noor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
  • Patent number: 11917929
    Abstract: Various embodiments described herein provide for a topological quantum computer that uses edge Majorana quasi-particles to form qubits. An inverted Indium Arsenide (InAs) and Gallium Antimonide (GaSb) heterostructure is disclosed that is a quantum spin Hall insulator. A layer of aluminum can be deposited over a nanotube that is placed across the layers of the heterostructure. Once the nanotube is removed, and a gate is formed on the heterostructure and the heterostructure is cooled so that the aluminum becomes superconducting, helical edge states are formed at the junction of the super conducting aluminum, the InAs, and the GaSb which creates a Majorana zero modes (MZMs) at zero magnetic field. The MZMs can be used to construct a topological qubit for fault-resistant topological quantum computation.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: February 27, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Wei Pan
  • Patent number: 11917928
    Abstract: Methods, apparatuses, and devices for Josephson junction preparation includes: obtaining a first pattern structure for generating a first Josephson junction of a first type and a plurality of second pattern structures for generating a plurality of second Josephson junctions of a second type; evaporating a material on the first pattern structure and the plurality of second pattern structures based on a first evaporation direction to generate a first electrode layer for implementing information transmission; forming an insulating layer on the first electrode layer, the insulating layer including a compound corresponding to the material; evaporating the material on the first pattern structure and the plurality of second pattern structures based on a second evaporation direction to generate a second electrode layer for implementing information transmission; and forming the first Josephson junction and the plurality of second Josephson junctions.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: February 27, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Ran Gao, Jin Qin, Chunqing Deng
  • Patent number: 11915100
    Abstract: A resonator, an oscillator, and a quantum computer capable of preventing oscillation conditions for generating a parametric oscillation from becoming complicated are provided. A resonator includes at least one loop circuit in which a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction are connected in a ring shape, in which critical current values of the first and second Josephson junctions are different from each other.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 27, 2024
    Assignee: NEC CORPORATION
    Inventors: Tomohiro Yamaji, Tsuyoshi Yamamoto
  • Patent number: 11910730
    Abstract: A superconducting circuit having a Josephson junction includes a first electrode layer for signal transmission; a second electrode layer for signal transmission; and an insulating layer arranged between the first electrode layer and the second electrode layer to form a Josephson junction, wherein, the first electrode layer and the second electrode layer are composed of a preset material, the insulating layer is composed of a compound corresponding to the preset material, and the preset material includes a non-aluminum superconducting material to prolong a coherence time of superconducting qubits.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 20, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Xiaohang Zhang, Wenlong Yu, Hsiang-Sheng Ku, Jingwei Zhou
  • Patent number: 11908701
    Abstract: A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christine Y Ouyang, Li-Te Lin