Abstract: A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.

Abstract: A filter for infrared radiation is provided as a photonic cooler coating. The filter for infrared radiation includes a first metal oxide; a second metal oxide; and a metal layer, wherein the first metal oxide layer is provided between the second metal oxide layer and the metal layer.

Abstract: The optical device includes a first photodiode, a second photodiode, and a hybrid absorber. The hybrid absorber is disposed above the first photodiode and the second photodiode. The hybrid absorber includes a color filter layer and a plurality of metal-insulator-metal structures. The color filter layer includes a first color filter disposed on the first photodiode and a second color filter disposed on the second photodiode, in which the first color filter is different from the second color filter. The plurality of metal-insulator-metal structures are disposed above the first photodiode and free of disposed above the second photodiode.

Abstract: A light emitter, comprising light emitting devices mechanically interconnected by a common substrate and an interconnection submount. The light emitting devices are electrically interconnected by the submount to provide an array of serially connected subsets of light emitting devices, each subset comprising at least three light emitting devices electrically connected in parallel. Also, a light emitter comprising first light emitting devices mechanically interconnected by a first common substrate, and second light emitting devices mechanically interconnected by a second common substrate, the first light emitting devices being mechanically and electrically connected to the second light emitting devices.

Abstract: A vertical Josephson Junction (JJ) qubit device that is fabricated from crystalline silicon material is provided. The JJ device has a substrate of epitaxial silicon, a lower superconducting electrode that is a superconducting region of the epitaxial silicon and an upper superconducting electrode of a metallic superconductor. The JJ device also has a junction layer. A section of the junction layer between the lower and upper superconducting electrodes forms a junction of the JJ device. Resonator and/or capacitor wiring of the JJ device is also fabricated using the metallic superconductor. The superconducting region is epitaxial silicon that is doped or implanted with boron or gallium. The substrate, the junction layer, and the implanted epitaxial silicon share a contiguous crystalline structure.

Abstract: A display panel, a manufacturing method thereof, and a display terminal are provided. The display panel includes a substrate layer, an anode layer, a pixel separating layer, an organic light-emitting layer, and a cathode layer. The pixel separating layer includes a plurality of pixel opening regions and a non-opening region disposed between two adjacent pixel opening regions. The cathode layer includes at least one via hole corresponding to the non-opening region of the pixel separating layer.

Abstract: A printed circuit board includes a wiring board including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers, a first die embedded in the plurality of insulating layers, a bridge embedded on the first die in the plurality of insulating layers, a second die mounted on the wiring board, and a third die mounted on the wiring board.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a semiconductor channel layer, a gate dielectric layer, a source terminal and a drain terminal. The semiconductor channel layer is disposed over and above the gate. The gate dielectric layer is disposed between the gate and the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. A contact plug is disposed on at least one of the source terminal and the drain terminal. A dielectric pattern surrounds the contact plug and covers the source terminal and the drain terminal. A gas barrier layer is disposed on the dielectric pattern and surrounding the contact plug.

Abstract: A modular quantum computer architecture is developed with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single modular register are accomplished using natural interactions between the qubits, and entanglement between separate modular registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. This architecture is suitable for the implementation of complex quantum circuits utilizing the flexible connectivity provided by a reconfigurable photonic interconnect network. The subject architecture is made fault-tolerant which is a prerequisite for scalability.

Abstract: Three-dimensional (3D) NAND memory structures and methods to manufacture 3D NAND memory structures are disclosed. A method includes forming a stack of layers that includes a first sub-stack for a transistor structure and a second sub-stack for a memory structure positioned on the first sub-stack. The second sub-stack includes at least one layer of conductive material and at least one layer of non-conductive material. The first sub-stack and the second sub-stack are separated by at least one non-conductive layer. The method includes forming a channel opening in the stack of layers, forming a gate dielectric in the channel opening, and providing a channel structure within the channel opening. The channel structure includes a semiconductive-behaving material and aligned with the transistor structure. The method includes providing a charge trap layer within the channel opening and aligned with the memory structure.

Abstract: There is disclosed an ultraviolet (UV) photo sensing element comprising a GaN substrate and a Ta2O5 thin film layer, forming a GaN (gallium-nitride) and Ta2O5 (tantalum pentoxide) based heterojunction wherein the formed heterojunction receives and converts UV light into electrical signals/in the photovoltaic mode (at 0 V) or in a self-driven mode. Also disclosed is a method of fabrication of an ultraviolet (UV) photodetector (PD) device, the method comprising growing silicon-doped n-type GaN epitaxial layers on a stack of un-doped GaN/sapphire samples, cleaning the GaN samples, pelletizing and depositing tantalum pentoxide (Ta2O5) powder on the n-type GaN samples, forming Ta2O5/GaN stacks, post-annealing the formed Ta2O5/GaN stacks; and depositing high purity Au on the Ta2O5/GaN stacks. The photodetector (PD) device is a heterojunction ultraviolet (UV) photodetector (PD) device.

Abstract: The present disclosure describes non-classical (e.g., quantum) computing systems and methods that utilize dopant molecules contained in host materials as qubits.

Abstract: A display device includes a substrate including a display area and a non-display area, a pixel circuit portion disposed on the substrate and including a transistor that drives a pixel, and a display element portion disposed on the pixel circuit portion and including a pixel electrode electrically connected to an electrode of the transistor through a bridge pattern. The pixel circuit portion includes a first capping layer disposed between the bridge pattern and the pixel electrode, and the pixel electrode and the bridge pattern are multiple metal layers including a same material.

Abstract: A semiconductor package includes a first semiconductor chip, which includes a first semiconductor substrate and a first bonding layer on the first semiconductor substrate. A second semiconductor chip includes a second semiconductor substrate, a second bonding layer bonded to the first bonding layer, and a chip-through-via which penetrates the second semiconductor substrate and is connected to the second bonding layer. A passivation film extends along an upper side of the second semiconductor chip and does not extend along side-faces of the second semiconductor chip. The chip-through-via penetrates the passivation film. A multiple-gap-fill film extends along the upper side of the first semiconductor chip, the side faces of the second semiconductor chip, and the side faces of the passivation film. The multiple-gap-fill films includes an inorganic filling film and an organic filling film which are sequentially stacked on the first semiconductor chip.

Abstract: A colour micro-LED display apparatus comprises an array of reflective optical elements and an array of micro-LED pixels with a uniform emission colour across the array arranged between the army of reflective optical elements and an output substrate. Light from the micro-LEDs is directed into the reflective optical elements and is incident on scattering regions in the apparatus. Colour converted scattered light is transmitted by the output substrate. A thin and efficient display apparatus may be provided with high spatial and angular colour uniformity and long lifetime.

Abstract: The various embodiments described herein include methods for manufacturing superconductor devices. A method for manufacturing superconductors may include: (i) generating spectra data from a first superconductor device; (iii) identifying a first peak ratio between a first phase peak and a second phase peak in the spectra data; (iv) generating additional spectra data from a second superconductor device; (v) identifying a second peak ratio of the additional spectra data from the second superconductor device; (vi) adjusting a manufacturing parameter based on the first peak ratio and the second peak ratio; and (vii) manufacturing a third superconductor device based on the adjusted manufacturing parameter.

Abstract: A display device according to some embodiments includes a substrate, a first power line extending in a first direction on the substrate, and configured to transmit a first alignment signal or a first driving voltage, a second power line extending in the first direction on the substrate, and configured to transmit a second alignment signal or a second driving voltage, a first electrode extending in a second direction that is substantially perpendicular to the first direction, configured to receive the first alignment signal or the first driving voltage, and electrically connected to the first power line, a second electrode spaced apart from the first electrode, extending in the second direction, configured to receive the second alignment signal or the second driving voltage, and electrically connected to the second power line, and a light emitting element between the first electrode and the second electrode.

Abstract: A display apparatus includes: a substrate including a main display area, a component area, and a peripheral area; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being disposed on the main display area; an auxiliary display element disposed on the component area; an auxiliary pixel circuit arranged on the peripheral area; and a connection line connecting the auxiliary display element to the auxiliary pixel circuit. The auxiliary display element includes an auxiliary pixel electrode that is at least partially round. The auxiliary pixel electrode has an asymmetrical shape with a contact portion at one side thereof. The contact portion is connected to the connection line.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.