Abstract: A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.

Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of layers on a base piezoelectric layer. The stack of layers includes a base metal film over the base piezoelectric layer; a first piezoelectric film over the base metal film; and a first metal film having an opening therein over the first piezoelectric film. The method also includes forming a trench in the stack of layers, wherein the trench passes through the opening in the first metal film but does not expose the base metal film; after forming the trench, forming a spacer structure under the first metal film but spaced apart from the base metal film; after forming the spacer structure, deepening the trench to expose the base metal film; and forming a contact in the trench.

Abstract: Systems and techniques that facilitate mode-selective couplers for frequency collision reduction are provided. In various embodiments, a device can comprise a control qubit. In various aspects, the device can comprise a first target qubit coupled to the control qubit by a first mode-selective coupler. In various instances, the first mode-selective coupler can facilitate A-mode coupling between the control qubit and the first target qubit. In various embodiments, the device can comprise a second target qubit coupled to the control qubit by a second mode-selective coupler. In various aspects, the second mode selective coupler can facilitate B-mode coupling between the control qubit and the second target qubit. In various embodiments, the first mode-selective coupler can comprise a capacitor that capacitively couples a middle capacitor pad of the control qubit to a middle capacitor pad of the first target qubit.

Abstract: Systems and techniques that facilitate space-saving coupler arm arrangement for superconducting qubits are provided. In various embodiments, a device can comprise a superconducting qubit. In various aspects, the superconducting qubit can be capacitively coupled to two or more coupler arms. In various instances, a parasitic capacitance between the two or more coupler arms can be within an order of magnitude of a capacitance between the superconducting qubit and at least one of the two or more coupler arms. In various cases, the parasitic capacitance can arise due to a physical proximity between the two or more coupler arms.

Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

Abstract: A semiconductor chip includes: a memory cell having a bit line, a word line, and a power supply node; first, second and third conductive lines formed in first, second and third conductive layers, respectively, the bit line including a portion of the first conductive line; the word line including a portion of the second conductive line; and the power supply node including a portion of the third conductive line; wherein the second conductive line has a thickness which is thicker than those of the first conductive line and the third conductive line, and the first, second and third conductive layers are stacked with one another. The first conductive line is longer than the second conductive line substantially along a first direction. The second conductive line is longer than the first conductive line substantially along a second direction orthogonal to the first direction.

Abstract: Apparatus and methods for performing qubit readout. In one aspect, an apparatus includes a qubit that operates at a qubit frequency; a frequency controller that is configured to control the qubit frequency and that during a qubit measurement operation is configured to: determine a compensation pulse that when applied to the qubit, counteracts qubit frequency changes during the qubit measurement operation; and apply the determined compensation pulse to the qubit during the qubit measurement operation to maintain the qubit frequency.

Abstract: In an embodiment an optoelectronic lighting device includes a carrier, exactly one light-emitting optoelectronic semiconductor component, wherein the semiconductor component has a light emission area on at least one surface side, and wherein the semiconductor component is arranged on an upper side of the carrier, at least one functional layer arranged above the light emission area and/or adjacent to the light emission area and an edging for the functional layer, wherein the edging surrounds the functional layer when viewed in a circumferential direction, the circumferential direction being parallel to the upper side of the carrier around the functional layer, and wherein the edging is formed of a transparent material.

Abstract: A system that includes: an array of qubits, each qubit of the array of qubits comprising a first electrode corresponding to a first node and a second electrode corresponding to a second node, wherein, for a first qubit in the array of qubits, the first qubit is positioned relative to a second qubit in the array of qubits such that a charge present on the first qubit induces a same charge on each of the first node of the second qubit and the second node of the second qubit, such that coupling between the first qubit and the second qubit is reduced, and wherein none of the nodes share a common ground is disclosed.

Abstract: An avalanche photodiode includes a silicon layer on a substrate; a germanium layer on the silicon layer; a cathode and an anode on any of the silicon layer and the germanium layer; and a plurality of contacts on the germanium layer, in addition to the cathode and the anode. The silicon layer can include a highly doped region at each end, an intrinsic doped region in a middle, and an intermediately doped region between the highly doped region at each end and the intrinsic doped region, and the cathode and the anode are each at a respective a highly doped region at each end. The germanium layer can include a plurality of highly doped regions with each including one of the plurality of contacts.

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate protection of a substrate in a qubit device using sacrificial material are provided. According to an embodiment, a device can comprise a superconducting lead provided on a pillar of a sacrificial material provided on a substrate. The device can further comprise a collapsed superconducting junction provided on the substrate and coupled to the superconducting lead.

Abstract: The present application provides an optical semiconductor device with a composite intervening structure. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. The intervening structure is disposed on the back surface of the memory die.

Abstract: A Josephson Junction qubit device is provided. The device includes a substrate of silicon material. The device includes first and second electrodes of superconducting metal. The device may include a nanowire created by direct ion implantation on to the silicon material to connect the first and second electrodes. The device may include first and second superconducting regions created by direct ion implantation on to the silicon material, the first superconducting region connecting the first electrode and the second superconducting region connecting the second electrode, with a silicon channel formed by a gap between the first and second superconducting regions.

Abstract: A quantum computing system includes a dilution refrigerator having a plurality of chambers. A trapped ion computing device includes a first set of qubits in a given chamber of the plurality of chambers of the dilution refrigerator. A superconducting computing device having a second set of superconducting qubits is inside the given chamber of the plurality of chambers of the dilution refrigerator.

Abstract: Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device.

Abstract: A hybrid classical-quantum computing device to execute a quantum circuit corresponding to a variational problem, is configured. The configuring further comprises causing the hybrid classical-quantum computing device to execute the quantum circuit by performing an adiabatic progression operation, wherein the adiabatic progression operation comprises increasing the difficulty of the variational problem from a simplified version of the problem to the variational problem.

Abstract: The present disclosure is directed to a sensor die with an embedded light sensor and an embedded light emitter as well as methods of manufacturing the same. The light emitter in the senor die is surrounded by a resin. The sensor die is incorporated into semiconductor device packages as well as methods of manufacturing the same. The semiconductor device packages include a first optically transmissive structure on the light sensor of the sensor die and a second optically transmissive structure on the light emitter of the sensor die. The first optically transmissive structure and the second optically transmissive structure cover and protect the light sensor and the light emitter, respectively. A molding compound is on a surface of a sensor die and covers sidewalls of the first and second optically transmissive structures on the sensor die.

Abstract: A display apparatus includes a base substrate, an active pattern disposed on the base substrate, a gate insulation layer disposed on the active pattern, a gate electrode disposed on the gate insulation layer and overlapping the active pattern, a first insulation layer disposed on the gate electrode and having a total amount of hydrogen of about 5 atomic percent (at. %) to about 30 at. %, and a source electrode and a drain electrode which are disposed on the first insulation layer and are electrically connected to the active pattern.

Abstract: A hybrid classical-quantum computing device to execute a quantum circuit corresponding to a variational problem, is configured. The configuring further comprises causing the hybrid classical-quantum computing device to execute the quantum circuit by performing an adiabatic progression operation, wherein the adiabatic progression operation comprises increasing the difficulty of the variational problem from a simplified version of the problem to the variational problem.

Abstract: A plurality of photoelectric converters is formed on a semiconductor substrate and performs photoelectric conversion according to incident light. A light path portion includes a transparent film through which the incident light is transmitted, a light-blocking wall for each of the plurality of photoelectric converters, the light-blocking wall partitioning the transparent film in a direction perpendicular to the semiconductor substrate, and blocking light, and a light-blocking film at an end of the light-blocking wall, the end being opposite to an end of the light-blocking wall that is closer to the semiconductor substrate, the light-blocking film having a film shape parallel to the semiconductor substrate, and including, for each of the plurality of photoelectric converters, an opening through which the incident light is transmitted.