Abstract: Various embodiments of the present disclosure are directed towards a method for forming a microelectromechanical systems (MEMS) device. The method includes forming a filter stack over a carrier substrate. The filter stack comprises a particle filter layer having a particle filter. A support structure layer is formed over the filter stack. The support structure layer is patterned to define a support structure in the support structure layer such that the support structure has one or more segments. The support structure is bonded to a MEMS structure.

Abstract: A method of forming a high voltage optical transformer includes forming a via through a transparent carrier wafer, forming a conductive layer within the via, bonding a solid state lighting (SSL) package to a first side of the carrier wafer, and bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side. The photovoltaic wafer may include an active area and a conductive area located outside of the active area that is in electrical contact with the conductive layer. The method further includes forming both an SSL contact with the solid state lighting package and a PV contact with the conductive layer on the same side of the carrier wafer.

Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.

Abstract: Techniques regarding encapsulating one or more superconducting devices of a quantum processor are provided. For example, one or more embodiments described herein can regard a method that can comprise depositing a metal fluoride layer onto a superconducting resonator and a silicon substrate that can be comprised within a quantum processor. The superconducting resonator can be positioned on the silicon substrate. Also, the metal fluoride layer can coat the superconducting resonator.

Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.

Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

Abstract: Techniques for quantum error correction of a multi-level system are provided and described. In some aspects, techniques for encoding a state of a multi-level quantum system include encoding a quantum information in a two-mode state of two quantum mechanical oscillators. Techniques for protecting the two-mode state against dephasing and energy loss are described.

Abstract: A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.

Abstract: A quantum processing unit is disclosed. The quantum processing unit includes at least one superconducting qubit that is based on phase-biased linear and non-linear inductive-energy elements. A superconducting phase difference across the linear and non-linear inductive-energy elements is biased, for example, by an external magnetic field, such that quadratic potential energy terms of the linear and non-linear inductive-energy elements are cancelled at least partly. In a preferred embodiment, such cancellation is at least 30%. The partial cancellation of the quadratic potential energy terms makes it possible to implement a high-coherence high-anharmonicity superconducting qubit design.

Abstract: Provided herein are metal structures that may include a cobalt alloy, a nickel alloy, or nickel, as well as related devices and methods. The metal structures may be formed by chemical vapor deposition (CVD), and may include trace amounts of precursor materials used during the CVD process.

Abstract: A quantum computing (QC) system that includes a plurality of qubits arranged substantially in a plurality of substantially planar regions that are substantially parallel to one another, at least some of the substantially planar regions including two or more qubits and one or more qubits of each substantially planar region configured to interact with one or more qubits of at least one other substantially planar region.

Abstract: Systems, computer-implemented methods, and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a first antenna can be positioned above a superconducting qubit chip having a first Josephson junction and a second Josephson junction. The first antenna can direct a first electromagnetic wave toward the first Josephson junction. A first length of a first defined vertical gap, between the first antenna and the superconducting qubit chip, can be sized to cause the first electromagnetic wave to circumscribe a first set of one or more capacitor pads of the first Josephson junction, thereby annealing the first Josephson junction, without annealing the second Josephson junction. In another example, the first length of the first defined vertical gap can be a function of a model of the first electromagnetic wave as a cone, wherein the cone originates from the first antenna and extends toward the superconducting qubit chip.

Abstract: A superconducting complex quantum computing circuit includes a circuit substrate in which a wiring pattern of a circuit element including quantum bits and measurement electrodes, and ground patterns are formed, and through-electrodes connecting the ground pattern formed on a first surface of the substrate surface and the ground pattern formed on a second surface; a first ground electrode including a first contact portion in contact with the ground patterns, and a first non-contact portion having a shape corresponding to a shape of the wiring pattern; a second ground electrode including a second contact portion in contact with the ground pattern; a control signal line provided with a contact spring pin at a tip; and a pressing member that presses the first ground electrode against the first surface of the circuit substrate or presses the second ground electrode against the second surface of the circuit substrate.

Abstract: A monofilament (100) for producing an Nb3Sn-containing superconductor wire (33) includes a powder core (1) with an Sn-containing powder, a reaction tube (3) composed of an Nb alloy that includes Nb and at least one further alloy component X. The powder core is disposed within the reaction tube. The monofilament also includes at least one source (4) for at least one partner component Pk. A respective source includes one or more source structures at a unitary radial position in the monofilament. The alloy component X and the partner component Pk form precipitates XPk on reaction annealing of the monofilament in which Sn from the powder core and Nb from the reaction tube react to produce Nb3Sn. The powder core is disposed in a moderation tube, which in turn is disposed within the reaction tube. This provides a monofilament for a powder-in-tube based Nb3Sn-containing superconductor wire with improved current carrying capacity.

Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which relate to the field of quantum computing. The superconducting circuit structure includes: at least two qubits; a connector, coupled with the two qubits respectively, to realize transversal coupling with each of the two qubits; and a coupler, coupled with the two qubits respectively, to realize longitudinal coupling with each of the two qubits. Therefore, the ?z?z parasitic coupling between the qubits is effectively removed, and a two-qubit gate with high fidelity is obtained.

Abstract: Apparatus, methods, and systems are disclosed for robust scalable topological quantum computing. Quantum dots are fabricated as van der Waals heterostructures, supporting localized topological phases and non-Abelian anyons (quasiparticles). Large bandgaps provide noise immunity. Three-dot structures include an intermediate quantum dot between two computational quantum dots. With the intermediate quantum dot in an OFF state, quasiparticles at the computational quantum dots can be isolated, with long lifetimes. Alternatively, the intermediate quantum dot can be controlled to decrease the quasiparticle tunneling barrier, enabling fast computing operations. A computationally universal suite of operations includes quasiparticle initialization, braiding, fusion, and readout of fused quasiparticle states, with, optionally, transport or tunable interactions—all topologically protected. Robust qubits can be operated without error correction.

Abstract: A colour micro-LED display apparatus comprises an array of reflective optical elements and an array of micro-LED pixels with a uniform emission colour across the array arranged between the array of reflective optical elements and an output substrate. Light from the micro-LEDs is directed into the reflective optical elements and is incident on scattering regions in the apparatus. Colour converted scattered light is transmitted by the output substrate. A thin and efficient display apparatus may be provided with high spatial and angular colour uniformity and long lifetime.

Abstract: A piezoelectric sensor (10) having an elongated-sheet shape includes a piezoelectric layer (11) containing an elastomer and piezoelectric particles and electrode layers (12a and 12b) which are disposed with the piezoelectric layer (11) sandwiched between the electrode layers. In the piezoelectric sensor (10), a pressure sensing region (S) has a length of 500 mm or longer in a longitudinal direction thereof; the electrode layers (12a and 12b) contain an elastomer and flaky conductive materials and are capable of elongating by 10% or more in one direction of plane directions; and when a space between one end portion (A) and the other end portion (B) of the pressure sensing region (S) in the longitudinal direction is set as a measurement zone, an electrical resistance in the measurement zone in the electrode layers (12a and 12b) is 3,000? or lower, and the specific Expression (I) is satisfied.

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures.

Abstract: The various embodiments described herein include methods for manufacturing superconductor devices. In some embodiments, a method of manufacturing a superconductor includes: (1) manufacturing a first superconductor device; (2) characterizing the first superconductor device, including: (a) obtaining x-ray diffraction spectra of the first superconductor device; and (b) identifying a ratio of a first cubic phase peak to a second cubic phase peak in the x-ray diffraction spectra; (3) adjusting a manufacturing parameter based on the identified ratio; and (4) manufacturing a second superconductor device with the adjusted manufacturing parameter.