Patents Examined by Matthew L. Reames
  • Patent number: 11917929
    Abstract: Various embodiments described herein provide for a topological quantum computer that uses edge Majorana quasi-particles to form qubits. An inverted Indium Arsenide (InAs) and Gallium Antimonide (GaSb) heterostructure is disclosed that is a quantum spin Hall insulator. A layer of aluminum can be deposited over a nanotube that is placed across the layers of the heterostructure. Once the nanotube is removed, and a gate is formed on the heterostructure and the heterostructure is cooled so that the aluminum becomes superconducting, helical edge states are formed at the junction of the super conducting aluminum, the InAs, and the GaSb which creates a Majorana zero modes (MZMs) at zero magnetic field. The MZMs can be used to construct a topological qubit for fault-resistant topological quantum computation.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: February 27, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Wei Pan
  • Patent number: 11915100
    Abstract: A resonator, an oscillator, and a quantum computer capable of preventing oscillation conditions for generating a parametric oscillation from becoming complicated are provided. A resonator includes at least one loop circuit in which a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction are connected in a ring shape, in which critical current values of the first and second Josephson junctions are different from each other.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 27, 2024
    Assignee: NEC CORPORATION
    Inventors: Tomohiro Yamaji, Tsuyoshi Yamamoto
  • Patent number: 11910730
    Abstract: A superconducting circuit having a Josephson junction includes a first electrode layer for signal transmission; a second electrode layer for signal transmission; and an insulating layer arranged between the first electrode layer and the second electrode layer to form a Josephson junction, wherein, the first electrode layer and the second electrode layer are composed of a preset material, the insulating layer is composed of a compound corresponding to the preset material, and the preset material includes a non-aluminum superconducting material to prolong a coherence time of superconducting qubits.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 20, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Xiaohang Zhang, Wenlong Yu, Hsiang-Sheng Ku, Jingwei Zhou
  • Patent number: 11908701
    Abstract: A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christine Y Ouyang, Li-Te Lin
  • Patent number: 11907805
    Abstract: A three-dimensional superconducting qubit and a method for manufacturing the same are disclosed. In an example, a three-dimensional superconducting qubit comprises a structural base comprising one or more insulating materials, and superconductive patterns on surfaces of the structural base. The superconductive patterns form at least a capacitive part and an inductive part of the three-dimensional superconducting qubit. A first surface of the surfaces of the structural base defines a first plane and a second surface of the surfaces of the structural base defines a second plane, the second plane being oriented differently than the first plane. At least one superconductive pattern of the superconductive patterns extends from the first surface to the second surface.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 20, 2024
    Assignee: IQM Finland Oy
    Inventors: Caspar Ockeloen-Korppi, Tianyi Li, Wei Liu, Vasilii Sevriuk, Tiina Naaranoja, Mate Jenei, Jan Goetz, Kuan Yen Tan, Mikko Möttönen, Kok Wai Chan
  • Patent number: 11903330
    Abstract: The method of performing braiding operations can include providing a first Josephson junction including first gates. The method can include providing a second Josephson junction including second gates. The method can include tuning the first gates to dispose a first pair of Majorana fermions a first region. The method can include tuning the second gates to dispose a second pair of Majorana fermions in a second region. The method can include tuning the first gates to dispose a first Majorana fermion in the first region and to dispose a second Majorana fermion in a third region. The method can include tuning the second gates to dispose a third Majorana fermion in a fourth region and to dispose a fourth Majorana fermion in the second region.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 13, 2024
    Assignee: NEW YORK UNIVERSITY
    Inventors: Javad Shabani, Matthieu C. Dartiailh
  • Patent number: 11887667
    Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, Albert Fayrushin, Matthew J. King, Madison D Drake
  • Patent number: 11882771
    Abstract: Techniques and methods to form smooth metal layers deposited onto selected surfaces of Josephson junction devices are provided. For example, one or more embodiments described herein can comprise depositing a layer of a first material comprising metal atom species on a selected surface of a device layer; depositing a layer of a second material on a surface of the layer of first material; and performing plasma etching on the layer of second material and the layer of first material to form an etched surface of the layer of first material that is smoother than the surface of the layer of first material, as deposited.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn Jessica Pooley, Hongwen Yan, Gerald W. Gibson
  • Patent number: 11876128
    Abstract: A field effect transistor comprising: a first semiconductor structure, the first semiconductor structure having a channel layer; a second semiconductor structure, the second semiconductor structure is arranged on the first semiconductor structure, and the second semiconductor structure is stacked in sequence from bottom to top with a Schottky layer, a first etch stop layer, a wide recess layer, an ohmic contact layer, and a narrow recess, a wide recess is opened in the ohmic contact layer, so that the upper surface of the wide recess layer forms a wide recess area and the upper surface of the Schottky layer forms a narrow recess area; at least one delta-doped layer, a gate metal contact, the gate metal contact is formed inside the wide recess a source metal contact; and a drain metal contact, and the drain metal contact is located on the other side of the gate metal contact.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 16, 2024
    Inventor: Walter Tony Wohlmuth
  • Patent number: 11868849
    Abstract: A quantum controller comprises a quantum control pulse generation circuit and digital signal management circuit. The quantum control pulse generation circuit is operable to generate a quantum control pulse which can be processed by any of a plurality of controlled circuits, and generate a first digital signal which can be routed to any of the plurality of controlled circuits. The digital signal management circuit is operable to detect, during runtime, to which one or more of the plurality of controlled circuits the first digital signal is to be routed, to manipulate the first digital signal based on the one or more of the plurality of controlled circuits to which the first digital signal is to be routed, where the manipulation results in one or more manipulated digital signals, and to route the one or more manipulated digital signals to one or more of the plurality of controlled circuits.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 9, 2024
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan
  • Patent number: 11859310
    Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, the first initial doping level is then reduced to a second initial doping level of the first or low second conductivity type.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 2, 2024
    Assignee: Azur Space Solar Power GmbH
    Inventors: Clemens Waechter, Gregor Keller, Daniel Fuhrmann
  • Patent number: 11854833
    Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 26, 2023
    Assignee: Google LLC
    Inventors: Evan Jeffrey, Joshua Yousouf Mutus
  • Patent number: 11843054
    Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 12, 2023
    Assignee: Intel Corporation
    Inventors: Van H. Le, Seung Hoon Sung, Benjamin Chu-Kung, Miriam Reshotko, Matthew Metz, Yih Wang, Gilbert Dewey, Jack Kavalieros, Tahir Ghani, Nazila Haratipour, Abhishek Sharma, Shriram Shivaraman
  • Patent number: 11828820
    Abstract: A high-temperature three-dimensional Hall sensor with a real-time working temperature monitoring function includes a buffer layer, an epitaxial layer, and a barrier layer sequentially grown on a substrate. A high-density two-dimensional electron gas is induced by polarization charges in a potential well at an interface of heterojunctions of the epitaxial layer. A lower surface of the substrate includes a vertical Hall sensor for sensing a magnetic field parallel to a surface of a device. An upper surface of the barrier layer includes a “cross” horizontal Hall sensor for sensing a magnetic field perpendicular to the surface of the device.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 28, 2023
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Huolin Huang, Hui Zhang
  • Patent number: 11825751
    Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chung-Yi Chiu
  • Patent number: 11817525
    Abstract: A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The values of overlap integrals between different electron wavefunctions in a conduction band of the chirp layer can be less than 0.05 for intersubband transition energies greater than 1.0 eV, and/or the values of overlaps between electron wavefunctions and barrier centers in a conduction band of the chirp layer can be less than 0.3 nm?1, when the structure is biased at an operating potential. The chirp layer can comprise a short-period superlattice with alternating wide bandgap barrier layers and narrow bandgap well layers, wherein the thickness of the barrier layers, or the well layers, or the thickness of both the barrier and well layers changes throughout the chirp layer.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Silanna UV Technologies Pte Ltd
    Inventors: Norbert Krause, Guilherme Tosi
  • Patent number: 11817513
    Abstract: A photodetector designing method includes, according to various requirements required by an application equipped with a photodetector including a photoelectric conversion layer having a superlattice structure mostly composed of amorphous selenium, a step of determining a form of the photodetector; a step of determining a type of a substrate suitable for a wavelength to be detected by the photoelectric conversion layer among the requirements, a step of calculating a multiplication factor M representing an amplification gain generated in a process of tunneling in the superlattice structure, and a step of determining, as a layer thickness of the photoelectric conversion layer, a thickness obtained by multiplying a thickness per one layer of the superlattice structure by the number of layers NSL of the superlattice structure on the assumption that the multiplication factor M is approximate to the number of layers NSL.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: November 14, 2023
    Assignees: EIWA BUSSAN CO., LTD.
    Inventors: Ken Okano, Joshua Dumenkosi John
  • Patent number: 11817521
    Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 14, 2023
    Assignee: Raytheon Company
    Inventors: Andrew Clarke, David R. Rhiger, Chad W. Fulk, Stuart B. Farrell, James Pattison, Jeffrey M. Peterson, Chad M. Althouse
  • Patent number: 11816537
    Abstract: A modular quantum computer architecture is developed with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single modular register are accomplished using natural interactions between the qubits, and entanglement between separate modular registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. This architecture is suitable for the implementation of complex quantum circuits utilizing the flexible connectivity provided by a reconfigurable photonic interconnect network. The subject architecture is made fault-tolerant which is a prerequisite for scalability.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: November 14, 2023
    Assignees: University of Maryland, Duke University
    Inventors: Christopher Monroe, Jungsang Kim
  • Patent number: 11812672
    Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeokshin Kwon, Jaehyeong Lee, Insu Jeon