Abstract: A nonvolatile memory device includes an inserted electrode line disposed between a first and a second electrode lines and extending in parallel with the second electrode line. The inserted electrode line is coupled to the second electrode line. A first intermediate pattern disposed between the inserted electrode line and a second intermediate pattern is disposed between the inserted electrode line and the second electrode line. One of the first and second intermediate patterns is a variable resistor and the other of the first and second intermediate patterns is a selector. The first intermediate pattern covers a bottom surface and a portion of sidewalls of the inserted electrode line.

Abstract: A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.

Abstract: One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.

Abstract: A method of manufacturing an integrated circuit package substrate is disclosed. The method may include forming a hole through a substrate layer in the package substrate. The method also includes inserting a prefabricated coaxial wire segment into the hole. The prefabricated coaxial wire segment may include a signal conductor, a ground conductor that surrounds the signal conductor, and dielectric material interposed between the signal conductor and the ground conductor. Furthermore, an integrated circuit package is also disclosed.

Abstract: A thin film transistor is disclosed. The drain and source electrode layer of the thin film transistor is disposed on the substrate, in which the drain and source electrode layer is divided into a drain region and a source region. The semiconductor layer and the first insulating layer are disposed on the drain and source electrode layer, in which the first insulating layer has an upper limit of thickness. The second insulating layer is disposed on the semiconductor layer and the first insulating layer, in which the second insulating layer has a lower limit of thickness. The gate electrode layer is disposed on the second insulating layer. The passivation layer is disposed on the gate electrode layer, and the pixel electrode layer is disposed on the passivation layer.

Abstract: A lighting module for emitting mixed light comprises at least one first semiconductor element which emits unconverted red light, at least one second semiconductor element which emits converted greenish white light having a first conversion percentage, at least one third semiconductor element which emits greenish white light having a second conversion percentage that is smaller than the first conversion percentage, and at least one resistor element having a temperature-dependent electric resistance, the second semiconductor element being connected in parallel to the third semiconductor element.

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

Abstract: Disclosed are a light emitting device and a lighting system which uses a light emitting diode. The light emitting device includes a body which has a first and a second sidewall. The sidewalls have a first length and a corresponding third and fourth sidewalls. The third and fourth sidewalls are close to the first and second sidewalls and have a second length shorter than the first length, and a concave portion which has an open upper portion. A first lead frame is disposed in the concave portion of the body which includes a first cavity having a depth lower than a bottom of the concave portion. Also, a second lead frame is disposed in the concave portion of the body and includes a second cavity having a depth lower than the bottom of the concave portion. There is a gap part between the first and second lead frames. In the first cavity is a light emitting chip, and in the second cavity there is a light emitting chip.

Abstract: An OLED device is disclosed. The OLED device includes: a substrate defined into an active area in which a plurality of pixels are formed in a matrix shape, a GIP (gate-in-panel) area in which drive elements are formed, a ground contact area, and a seal line area; a thin film transistor formed in each pixel region within the active area; an organic light emission diode formed on a protective film and configured to include a first electrode, an organic light emission layer and a second electrode; a bank layer formed to divide the organic light emission diode into pixel units; a signal wiring formed in the ground contact area and the seal line area; and an extended portion formed from the same material as the first electrode of the organic light emission diode and configured to cover the signal wiring, wherein a seal line within in the seal line area is formed on an edge of the signal wiring, which is covered with the extended portion, and an interlayer insulation film adjacent to the edge of the signal wiring.

Abstract: An embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: The present invention relates to a substrate (1) comprising: a first segment (5a) provided with a first contact pad (22a) for connection of a first light emitting element (2a); and a second segment (5b) provided with a second contact pad (22b) for connection of a second light emitting element (2b), wherein the substrate is provided with at least one through-hole (6a-c) that extends from an edge (8,9) of the substrate to a point within the substrate, such that a relative movement, in a plane of the substrate, can be achieved between the first segment (5a) of the substrate and the second segment (5b) of the substrate by applying a mechanical force to the substrate. This makes very accurate alignment to a multiple cavity optical system possible without adjusting the optics, thereby enabling a more convenient and time efficient process in production.

Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

Abstract: A semiconductor module includes a semiconductor device; a metal plate portion that includes a first surface on a side of the semiconductor device and has a fastening portion at an end thereof; a molded portion that is formed by molding a resin on the semiconductor device and the metal plate portion, a cooling plate portion that is a separate member from the metal plate portion, is provided on a side opposite to the first surface on the side of the semiconductor device, and includes fins on a side opposite to the side of the metal plate portion; wherein the fastening portion of the metal plate portion is exposed out of the molded portion, and the cooling plate portion includes a fastening portion at a position that corresponds to a position of the fastening portion of the metal plate portion.

Abstract: A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.

Abstract: The present disclosure relates to a thin film transistor substrate having a metal oxide semiconductor for flat panel displays and a method for manufacturing the same. The present disclosure suggests a thin film transistor substrate including: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a source electrode overlapping with one side of the gate electrode on the gate insulating layer; a drain electrode being apart from the source electrode and overlapping with other side of the gate electrode on the gate insulating layer; an oxide semiconductor layer contacting an upper surface of the source electrode and the drain electrode, and extending from the source electrode to the drain electrode; and an etch stopper having the same shape with the oxide semiconductor layer, and contacting an upper surface of the oxide semiconductor layer.

Abstract: A cooling fin 9 is joined to a semiconductor element 1. A resin 10 encapsulates the semiconductor element 1. A portion of the cooling fin 9 projects from a lower surface of the resin 10. A cooler 11 has an opening 12. The cooling fin 9 projecting from the resin 10 is inserted in the opening 12 of the cooler 11. The lower surface of the resin 10 and the cooler 11 are joined to each other by a joining material 13 such as an adhesive. Therefore, a reduction in the number of component parts and a reduction in weight can be achieved, and compatibility between the heat conductivity and the strength of joining can be ensured.

Abstract: An array substrate includes: a substrate; a thin film transistor including a gate electrode, an oxide semiconductor layer and source and drain electrodes, wherein a first insulating layer of an inorganic insulating material is disposed between the gate electrode and the oxide semiconductor layer, and wherein a second insulating layer of an inorganic insulating material is disposed between the oxide semiconductor layer and the source and drain electrodes; a passivation layer on the thin film transistor; a first electrode on the passivation layer in the pixel region; and a first hydrogen absorbing layer on at least one of top and bottom surfaces of the first insulating layer, top and bottom surfaces of the second insulating layer and top and bottom surfaces of the passivation layer, the first hydrogen absorbing layer including plurality of particles spaced apart from each other and including one of nickel, palladium and platinum.

Abstract: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.

Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.