Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer.

Abstract: A semiconductor light-emitting element includes: a double-mesa structure of semiconductor formed to have a cylindrical cross section; an insulating member formed to fill a space surrounding the double-mesa structure, with the insulating member comprising a lower insulating member and an upper insulting member covering the lower insulating member; and a first electrode formed on the upper insulating member to come into contact with part of a top surface of the double-mesa structure. The lower insulating member has multiple lower air pillars that are formed in an area aligning with the first electrode, and the upper insulating member has multiple upper air pillars that are formed around the first electrode. It has low dielectric constant and reduced electrical parasitics especially parasitic capacitances, thereby improving high frequency performance and improving modulation speed of light-emitting device finally.

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.

Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.

Abstract: A reverse conducting semiconductor device includes a high-concentration anode layer and a barrier metal layer, the width of the high-concentration anode layer is set larger than the width of contact of the barrier metal layer and the high-concentration anode layer, thereby ensuring that the area of contact between the barrier metal layer and the high-concentration anode layer is constant.

Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Abstract: An optoelectronic device comprises a semiconductor stack, a first metal layer formed above the semiconductor stack, wherein the first metal layer comprises a first major plane and a first boundary with a gradually reduced thickness, and a second metal layer formed above the first metal layer, wherein the second metal layer comprise a second major plane paralleling to the first major plane and a second boundary with a gradually reduced thickness, and the second boundary of the second metal layer exceeds the first boundary of the first metal layer.

Abstract: Memory cells with recessed electrode contacts and methods of forming the same are provided. An example memory cell can include an electrode contact formed in a substrate. An upper surface of the electrode contact is recessed a distance relative to an upper surface of the substrate. A first portion of a memory element is formed on an upper surface of the electrode contact and the upper surface of the substrate.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: A thin film transistor substrate is disclosed, which comprises: a substrate; and plural thin film transistor units disposed on the substrate and respectively comprising: an active layer disposed on the substrate and made of polysilicon; an insulating layer disposed on the active layer; and a source electrode and a drain electrode disposed on the insulating layer, wherein the insulating layer comprises a first region corresponding to the active layer and a second region corresponding to a region outside the active layer, and a roughness of the first region is larger than that of the second region.

Abstract: An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality of dielectric layers underlying the first substrate. The second semiconductor chip includes a second substrate and a second plurality of dielectric layers over the second substrate, wherein the first and the second plurality of dielectric layers are bonded to each other. A metal pad is in the second plurality of dielectric layers. A redistribution line is over the first substrate. A conductive plug is electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad. A bottom surface of the second portion contacts a top surface of the metal pad.

Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current.

Abstract: A Ga2O3 semiconductor element includes: an n-type ?-Ga2O3 single crystal film, which is formed on a high-resistance ?-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type ?-Ga2O3 single crystal film; and a gate electrode, which is formed on the n-type ?-Ga2O3 single crystal film between the source electrode and the drain electrode.

Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

Abstract: A semiconductor structure includes a top gate, an oxide semiconductor channel layer, a first dielectric layer, a second dielectric layer, a source and a drain. The oxide semiconductor channel layer is disposed between the top gate and a substrate. The first dielectric layer is disposed between the top gate and the oxide semiconductor channel layer. The second dielectric layer is disposed between the first dielectric layer and the oxide semiconductor channel layer. The source and the drain are disposed on two opposite sides of the oxide semiconductor channel layer and located between the first dielectric layer and the substrate. A portion of the oxide semiconductor channel layer is exposed between the source and the drain. A portion of the first dielectric layer and a portion of the second dielectric layer directly contact with and entirely cover the portion of the oxide semiconductor channel layer.

Abstract: A magnetic element includes a first magnetic layer, a first non-magnetic layer on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer, the third magnetic layer having a side wall layer including a material which is included in the second non-magnetic layer; wherein the material is one of Ru and Pt as a common material to the side wall layer and the second non-magnetic layer.

Abstract: According to one embodiment, a photocoupler includes: an input terminal; a light emitting unit; a light receiving unit and an output terminal. An input electrical signal having a prescribed voltage is input into an input terminal. The light emitting unit is connected to the input terminal, includes a light emitting element configured to emit emission light, and is configured to drive the light emitting element under a constant voltage of the input electrical signal. The light receiving unit includes a light receiving element configured to receive the emission light and convert the emission light into an electrical signal. The output terminal is insulated from the input terminal and configured to output the electrical signal in accordance with the input electrical signal.

Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.