Abstract: A light emitting device according to an embodiment includes a body including first and second side walls which correspond to each other, third and fourth side walls which have lengths longer than lengths of the first and second side walls, and a concave portion; a first lead frame under the concave portion and the third side wall; a second lead frame under the concave portion and the fourth side wall; a light emitting chip on at least one of the first and second lead frames; a molding member on the concave portion; a first recess portion recessed from the first side wall toward the second side wall and connected to a bottom of the body; and a second recess portion recessed from the second side wall toward the first side wall and connected to the bottom of the body.

Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract: TFT substrate (10) includes a plurality of pixel regions each including light emitting regions of at least three colors, which light emitting regions include light emitting layers (23R(1), 23G, 23R(2), and 23B), respectively, and two adjacent ones of the light emitting regions are a combination other than a combination of (i) a light emitting region included in a light emitting layer (23G) of a color having a highest current efficiency in a case where the light emitting layers of the light emitting regions of the at least three colors emit light having an identical luminance and (ii) a light emitting region included in a light emitting layer (23B) of a color having a lowest current efficiency in a case where the light emitting layers of the light emitting regions of the at least three colors emit light having an identical luminance.

Abstract: According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select FET having a select gate electrode, and using the semiconductor layer as a channel.

Abstract: A chip stack package includes a first chip disposed over a substrate, a second chip disposed over the first chip and having an overhang, and a first supporter attached to a bottom surface of the overhang of the second chip and a sidewall of the first chip. The overhang of the second chip protrudes from the sidewall of the first chip.

Abstract: Provided is a nitride semiconductor light-emitting element having a low contact resistance between an n-type nitride semiconductor layer and an n-side electrode. A portion of the n-type nitride semiconductor layer is removed by a plasma etching process using a gas containing halogen to expose a surface region of the n-type nitride semiconductor layer. Next, such an exposed surface region is further subjected to a plasma treatment using a gas containing oxygen. After that, the n-side electrode formed of aluminum is formed so as to be in contact with the surface region. In the surface region, a carrier concentration is decreased from the inside of the n-type nitride semiconductor layer toward the n-side electrode.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: An array substrate is disclosed. The array substrate includes a non-display region surrounding a display region. The array substrate also includes gate lines in the display region, and a gate drive circuit and a bus electrically insulated from the gate lines and a gate drive circuit in the non-display region. The gate lines extend into the non-display region and are electrically connected to the gate drive circuit, and each of the gate lines crosses the bus in a first overlap region. The array substrate also includes auxiliary electrode line segments between the bus and the display region. The auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and the auxiliary electrode line segments are disposed in either of a same conductive layer as the bus, or a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed.

Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.

Abstract: An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs1-aSba where the ratio a is 0 or more and 0.05 or less, a second component layer formed of GaSb, and a third component layer formed of InSbxAs1-x where the ratio x is more than 0 and less than 1. The third component layer is disposed so as to be in contact with one main surface of the second component layer. The other main surface of the second component layer is in contact with the first component layer within the unit structure. The third component layer has a thickness of 0.1 nm or more and 0.9 nm or less.

Abstract: A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.

Abstract: A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.

Abstract: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).

Abstract: The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.