Abstract: A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Abstract: One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions. A first material layer is formed on the bottom of each of the plurality of first trenches such that the first material layer leaves at least one segment of at least one sidewall of each of the plurality of trenches uncovered. Each of the plurality of first trenches is filled by epitaxially growing a semiconductor material from the at least one uncovered sidewall segment. After filling the first trenches, second trenches are formed in the mesa regions.

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first insulating layer is disposed on a surface of the first trench. A second insulating layer is disposed in the first trench. A first conductive layer is disposed between the first and second insulating layers. A second conductive layer is disposed in the second trench. A third insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench.

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract: According to one embodiment, a non-volatile memory device includes a first stacked electrode provided above a underlying layer, a second stacked electrode juxtaposed with the first stacked electrode above the underlying layer, a plurality of first semiconductor layers piercing the first stacked electrode in a direction perpendicular to the underlying layer, and a second semiconductor layer piercing the second stacked electrode in a direction perpendicular to the underlying layer. The device further includes a memory film provided between the first stacked electrode and the first semiconductor layers, and between the second stacked electrode and the second semiconductor layer, and a link part provided between the underlying layer and the first stacked electrode, and between the underlying layer and the second stacked electrode. The link part is electrically connected to one end of each of the first semiconductor layers and one end of the second semiconductor layer.

Abstract: A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.

Abstract: Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.

Abstract: A Ga2O3 semiconductor element includes: an n-type ?-Ga2O3 single crystal film, which is formed on a high-resistance ?-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type ?-Ga2O3 single crystal film; and a gate electrode, which is formed on the n-type ?-Ga2O3 single crystal film between the source electrode and the drain electrode.

Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.

Abstract: A semiconductor DC transformer is provided. The semiconductor DC transformer comprises: a plurality of semiconductor electricity-to-light conversion structures connected in series for converting input electric energy into optical energy; and a plurality of semiconductor light-to-electricity conversion structures connected in series for converting input optical energy into electric energy, in which a number of the semiconductor electricity-to-light conversion structures is different from that of the semiconductor light-to-electricity conversion structures so as to realize a DC transformation, and a working light spectrum of the semiconductor electricity-to-light conversion structures is matched with that of the semiconductor light-to-electricity conversion structures.

Abstract: A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line.

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract: An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

Abstract: An all-electric spin field effect transistor is disclosed, which includes an injection node, injecting an electron in a first spin direction; a detection node, detecting the electron in the first spin direction; and a gate, disposed between the injection node and the detection node such that the electron changes from the first spin direction to a second spin direction by carrying out precession; if the second spin direction is parallel to the first spin direction, the electron is able to pass through the detection node; if the second spin direction is antiparallel to the first spin direction, the electron is unable to pass through the detection node.

Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.