Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on a first substrate a sequence of layers of semiconductor material forming a solar cell including at least a top subcell and a bottom subcell; mounting a surrogate substrate on top of the sequence of layers adjacent to the bottom subcell; removing the first substrate to expose the surface of the top subcell; removing the surrogate substrate; and holding the solar cell on a vacuum chuck to support it for subsequent fabrication operations, such as attaching interconnects to the solar cells to form an interconnected array.

Abstract: An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm?3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface.

Abstract: Silicon containing substrates are coated with nickel. The nickel is coated with a protective layer and the combination is heated to a sufficient temperature to form nickel silicide. The nickel silicide formation may be performed in oxygen containing environments.

Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.

Abstract: A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.

Abstract: In a semiconductor light emitting device, light is lost from a side surface of a substrate; therefore, if a substrate side surface occupies a large area, it decreases light extraction efficiency. The area of the substrate side surface may be reduced by reducing a thickness of the substrate. However, a thin substrate has low mechanical strength and is cracked by a stress during work process, and that decreases the yield. A light emitting layer is formed on a substrate. After fixed to a grinding board with wax, the substrate is ground to thin. A support substrate is then bonded to the substrate for reinforcement. The substrate is fixed to an electrode and others, with the support substrate bonded to the substrate. The support substrate is lastly removed.

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract: A defect inspecting method includes: forming, in a first air pressure state, a film, which covers one opening of two openings provided on an upper surface of a substrate, on a tubular contact hole formed on the substrate in manufacturing a semiconductor device and formed in a tubular shape by connecting two cylindrical contact holes on bottom surface sides thereof, both ends of the tubular shape being opened in the openings; exposing the substrate covered with the film in a second air pressure state; and observing whether the film is deformed to thereby inspect whether the part of the tubular shape is blocked.

Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: A method for making semiconductor electrodes includes provided a wafer. The wafer includes at least one conductive unit, a plurality of first connective units connected to the conductive unit, a plurality of first metal layers connected to the first connective units and a plurality of second connective units connected to the first metal layers. Photo-resist is provided on the first and second connective units. A second metal layer is provided on each of the first metal layers via using an electroplating device. The wafer is cut through the photo-resist, thus forming semiconductor electrodes.

Abstract: Electronic assemblies, especially one containing volatile memory, used a flexible membrane with conducting lines which acts as an intrusion sensor against chemical and mechanical attacks. The lines are fabricated from inherently conducting polymers which are solution processed and directly patterned. The material was applied to a flexible polymer film by spin coating and patterned by application of a resist, followed by exposure/development of the resist and transferring the image into the polyaniline by reactive ion etching techniques. The conducting lines have high conductivity, tranparency properties which made them difficult to detect and possess excellent adhesion to the substrate film, as well as to the potting material which enclosed the structure. They also offered lightweight advantages over conventionally filled materials. These materials can also be used in conjunction with conventional conductor materials to further enhance protection against intrusion by sophisticated mechanical means.

Abstract: A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

Abstract: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multichip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract: A method of producing a polymer composition for semiconductor optoelectronics, comprising the steps of providing at least one type of disilane monomer which is homo- or copolymerized to form a (co)polymer and then combined with nanoparticles to provide a polymer composition. The nanoparticle containing composition has excellent properties with high refractive index or dielectric constant.

Abstract: The present invention aims at providing: a material for forming an adhesion reinforcing layer which can reinforce the adhesion between a low dielectric constant film, especially a low dielectric constant film containing an inorganic material, and other members; an adhesion reinforcing layer formed by the said material and exhibits superior adhesion; a fast and highly reliable semiconductor device having the adhesion reinforcing layer; and a manufacturing method thereof. The material for forming an adhesion reinforcing layer contains at least any one of organoalkoxysilane having a basic functional group, a basic additive and organoalkoxysilane. The adhesion reinforcing layer is formed by the said material. The manufacturing method of a semiconductor device includes a process for forming a low dielectric constant film and, at least before or after the process for forming a low dielectric constant film, a process for forming an adhesion reinforcing layer with the said material.

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Abstract: There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer (11) and a second material layer (12) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer (12) or an interface thereof.

Abstract: Provided is a method of fabricating an image sensor device. The method includes providing a semiconductor substrate having a front side and a back side, forming a first isolation structure at the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side, and forming a second isolation structure at the back side of the semiconductor substrate. The first and second isolation structures are shifted with respect to each other.