Patents Examined by Matthew Smith
  • Methods for manufacturing MEMS sensor and thin film thereof with improved etching process
    Patent number: 7998776
    Abstract: A method for manufacturing a MEMS sensor and a thin film thereof includes steps of etching a top surface of a single-crystal silicon wafer in combination of a deposition process, an isotropic DRIE process, a wet etching process and a back etching process in order to form a pressure-sensitive single-crystal silicon film, a cantilever beam, a mass block, a front chamber, a back chamber and trenches connecting the front and the back chambers. The single-crystal silicon film is prevented from etching so that the thickness thereof can be well controlled. The method of the present invention can be used to replace the traditional method which forms the back chamber and the pressure-sensitive single-crystal silicon film from the bottom surface of the silicon wafer.
    Type: Grant
    Filed: October 23, 2010
    Date of Patent: August 16, 2011
    Assignee: Memsensing Microsystems Technology Co., Ltd.
    Inventors: Gang Li, Wei Hu
  • Method for fabricating semiconductor device
    Patent number: 7998825
    Abstract: A method for fabricating a semiconductor device includes: forming an etch stop pattern over a conductive layer, the etch stop pattern having a first opening exposing a top surface of the conductive layer; forming an insulation layer over the etch stop pattern; selectively etching the insulation layer to form a second opening exposing the top surface of the conductive layer; and enlarging the second opening until the etch stop pattern is exposed.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Han-Sang Song, Jong-Bum Park, Jong-Kook Park
  • Dicing/die bonding film
    Patent number: 7998552
    Abstract: A dicing die-bonding film in which the adhesive properties during the dicing step and the peeling properties during the pickup step are controlled so that both become good, and a production method thereof, are provided. The dicing die-bonding film in the present invention is a dicing die-bonding film having a pressure-sensitive adhesive layer on a base material and a die bond layer on the pressure-sensitive adhesive layer, in which the arithmetic mean roughness X (?m) on the pressure-sensitive adhesive layer side in the die bond layer is 0.015 ?m to 1 ?m, the arithmetic mean roughness Y (?m) on the die bond layer side in the pressure-sensitive adhesive layer is 0.03 ?m to 1 ?m, and the absolute value of the difference of the X and Y is 0.015 or more.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 16, 2011
    Assignee: Nittok Denko Corporation
    Inventors: Yasuhiro Amano, Sadahito Misumi, Takeshi Matsumura
  • Semiconductor device
    Patent number: 7999305
    Abstract: A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge storage insulating film, and a control gate electrode formed on the block insulating film, wherein a distance between the element region and the control gate electrode is shorter at a center portion of the unit gate structure than at both ends thereof, as viewed in a section parallel to a channel width direction.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Fujitsuka, Yoshio Ozawa, Katsuaki Natori
  • Method for fabricating low-k dielectric and Cu interconnect
    Patent number: 7998873
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Semiconductor device and manufacturing method thereof
    Patent number: 7999393
    Abstract: A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Endo, Tatsuya Kato
  • Method of manufacturing solid state imaging device, solid state imaging device, and camera using solid state imaging device
    Patent number: 7999291
    Abstract: A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer showing an oxidizing property at the time of film formation, the transparent layer being formed on the photo-electric conversion parts and the light-shielding layer.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: August 16, 2011
    Assignee: Sony Corporation
    Inventors: Takeshi Takeda, Tadayuki Dofuku, Kenji Takeo
  • Transistor device with two planar gates and fabrication process
    Patent number: 7994008
    Abstract: A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 9, 2011
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Romain Wacquez, Philippe Coronel, Damien Lenoble, Robin Cerutti, Thomas Skotnicki
  • Display device, manufacturing method thereof, and television receiver
    Patent number: 7993993
    Abstract: The present invention discloses a method for manufacturing a display device comprising the steps of forming a first film pattern using a photosensitive material over a substrate, forming a second film pattern in such a way that the first film pattern is exposed by being irradiated with a laser beam, modifying a surface of the second film pattern into a droplet-shedding surface, forming a source electrode and a drain electrode by discharging a conductive material to an outer edge of the droplet-shedding surface by a droplet-discharging method, and forming a semiconductor region, a gate-insulating film, and a gate electrode over the source electrode and the drain electrode.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Shunpei Yamazaki, Hironobu Shoji
  • Heterogeneous substrate including a sacrificial layer, and a method of fabricating it
    Patent number: 7993949
    Abstract: The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 9, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Perruchot, Bernard Diem, Vincent Larrey, Laurent Clavelier, Emmanuel Defay
  • Method of manufacturing silicon carbide self-aligned epitaxial MOSFET for high powered device applications
    Patent number: 7994017
    Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: August 9, 2011
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Kent Bertilsson, Andrei Konstantinov
  • Method of detecting heavy metal in semiconductor substrate
    Patent number: 7993942
    Abstract: A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a metal/oxide film/semiconductor junction element by using a mercury probe method; and a step of detecting and quantifying heavy metal by calculating the surface concentration of the heavy metal from junction capacitance characteristics of the element.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: August 9, 2011
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Semiconductor wafer with low-K dielectric layer and process for fabrication thereof
    Patent number: 7994069
    Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: August 9, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brad Smith, Cindy Goldberg, Robert E. Jones
  • Manufacturing method of semiconductor device
    Patent number: 7994006
    Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
  • Method for fabricating semiconductor device
    Patent number: 7994018
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate in succession, etching the second oxide film and the nitride film to form a second oxide film pattern and a nitride film pattern, exposing a portion of the first oxide film, performing at least one nitrogen implantation into the semiconductor substrate to form a nitrogen injection region under the exposed portion of the first oxide film, forming a third oxide film over the second oxide film pattern, the nitride film pattern, and the semiconductor substrate, forming a trench that is deeper than the nitrogen ion injection region by etching the semiconductor substrate using the second oxide film pattern as a mask, and filling the trench with an oxide film to form a device isolating film.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 9, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Doo Sung Lee
  • Method of manufacturing a flexible device and method of manufacturing a flexible display
    Patent number: 7989314
    Abstract: Provided are a method of separating a metal layer and an organic light emitting diode. A method of manufacturing a flexible device and a method of manufacturing a flexible display include forming a releasing layer on a substrate, forming a metal layer on the releasing layer, forming an insulating layer on the metal layer, forming a releasable layer on the insulating layer, bonding a plastic to the releasable layer, and separating the substrate and the releasing layer at an interface therebetween to manufacture a flexible device. Since the conventional process equipment using the glass substrate can be compatibly used, the manufacturing cost can be reduced. In addition, since the glass substrate has less limitation in the process temperature compared with the plastic substrate, an electric device having a superior performance can be manufactured.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: August 2, 2011
    Assignee: Postech Academy-Industry Foundation Pohang Univ. of Science & Technology
    Inventors: Jong Lam Lee, Soo Young Kim
  • Fusion bonding process and structure for fabricating silicon-on-insulation (SOI) semiconductor devices
    Patent number: 7989894
    Abstract: A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 500 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 500 angstrom thick oxide layer; providing a second semiconductor wafer having an oxide thereover; and, bonding the first semiconductor wafer oxide to the second semiconductor wafer oxide at an elevated temperature.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: August 2, 2011
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Anthony D. Kurtz, Alexander A. Ned
  • Heat extraction from packaged semiconductor chips, scalable with chip area
    Patent number: 7989949
    Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: August 2, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Vikas Gupta, Siva P Gurrum, Gregory E Howard
  • Semiconductor die singulation method
    Patent number: 7989319
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Michael J. Seddon
  • Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics
    Patent number: 7989352
    Abstract: By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: August 2, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner