Abstract: An insulation film-forming method comprising the steps of:(A-1) heating and evaporating silicon raw materials comprising SiOx (provided that 0.ltoreq.X.ltoreq.1.8);(A-2) vapor phase reacting the evaporated silicon raw materials and a gas including oxygen, and generating silicon dioxide;(A-3) adhering the silicon dioxide to a substrate surface, and forming a first insulation film comprising silicon dioxide on the surface substrate; and(B) forming a second insulation film comprising silicon dioxide on the first insulation film by a chemical vapor phase growth technique or sputter technique.

Abstract: Method of forming intermetallic insulating layers in semiconductor devices are disclosed, which not only have superior adhesion and homogeneous step coverage but also prevent the generation of voids due to the penetration of moisture. According to the method, metal interconnects are, first formed on the semiconductor substrate. Thereafter, a first insulating layer is formed to a thickness capable of sufficiently filling the spaces between the metal interconnects by reacting Tetraethylorthosilicate(TEOS) gas of a predetermined flow rate with O.sub.3 gas of a predetermined density in a CVD furnace. Next, a second insulating layer of a predetermined thickness is formed on the first insulating layer using the same furnace but by changing only the flow rate of TEOS.

Abstract: This invention provides a process for making an insulation layer for use in microelectronic devices, whereby capacitive coupling and propagation delay in the microelectronic devices are reduced. This invention can include the formation of a stable solution of spherical particles consisting of a ceramic core 10 and a non-polar coating 20. This solution can be applied to an microelectronic substrate, and dried to form a continuous, porous layer. Novel methods are disclosed for bonding these particles together into an integral layer. Porous layers formed by the process of this invention possess a very low dielectric constant, and can be produced using equipment and techniques common and available to those skilled in the art of microelectronic fabrication.

Abstract: A method of forming an isolating trench device in a semiconductor device comprising the steps of; sequentially forming a first material layer and a second material layer over a surface of a semiconductor substrate, exposing a portion of the semiconductor substrate in which a device isolation region is to be formed by selectively etching the first and second material layers, forming side wall spacers on exposed lateral sidewalls of the first and second material layers, forming a trench by etching the exposed portion of the semiconductor substrate using the side wall spacers as a mask, depositing an insulating film having an underlayer dependency characteristic over the surface of the resulting structure, etching the surface of the insulating film, and removing the first and second material layers.

Abstract: In a method for forming a groove-type isolation area, an insulating pattern is formed by a selective oxidation process or a LOCOS process on a semiconductor substrate. The semiconductor substrate is etched with a mask of the insulating pattern to create a groove in the semiconductor substrate. An insulating layer is buried in the groove to form the groove-type isolation area.

Abstract: A method for forming an oxide film over a spin-on-glass (SOG) layer by a plasma-enhanced chemical-vapor deposition (PECVD) is disclosed. The SOG layer is pre-processed in a forming gas of hydrogen and nitrogen in a PECVD chamber. Then the oxide film is formed over the SOG layer by means of the PECVD process in the PECVD chamber.

Abstract: The present invention provides a method of manufacturing of planarizing an insulating layer using a sized reversed interconnect mask and two polish stop layers. Spaced interconnections 14 are provided over the semiconductor substrate 10. An insulating layer 22 is formed over the interconnections 14 forming valleys 18 between the spaced interconnections 14. A first polish stop layer 26 is formed over the insulating layer 22. A dielectric layer 30 is formed over the first polish stop layer 26. A second polish stop layer 36 is formed over the dielectric layer 30. The top of the second polish stop layer 36 over the valley 23 is coplanar with the top of the first polish stop layer 26 over the interconnect 14. A reduced size, reverse interconnect mask 40 is formed over the second polish stop layer 36. The reduced size, reverse interconnect mask 40 covers portions of the valleys 23 between the spaced interconnections 14.

Abstract: On manufacturing a semiconductor device comprising a semiconductor substrate having a principal surface and an objective oxide film on the semiconductor substrate, the semiconductor substrate is subjected to a heat treatment in an oxidizing atmosphere for a predetermined time duration to form a provisional oxide film on the principal surface at a first step. Subsequently, at a second step, the provisional oxide film is removed to expose the semiconductor substrate as an exposed surface of the semiconductor substrate by placing in a reducing atmosphere the semiconductor substrate with the provisional oxide film formed on the semiconductor substrate. Thereafter, the objective oxide film is formed on the exposed surface of the semiconductor substrate. Preferably, the heat treatment is carried out in the oxidizing atmosphere of an oxygen-partial pressure not higher than 5% at a temperature not lower than 950.degree. C. for the predetermined time duration which is not shorter than fourty minutes.

Abstract: A method for avoiding oxide peeling by removing polymer contaminants from the edge of a wafer is described. An interlevel dielectric sandwich layer is formed by depositing a first oxide layer overlying semiconductor device structures in and on a semiconductor substrate, coating a spin-on-glass layer overlying the first oxide layer and rinsing the spin-on-glass layer whereby an edge bead rinse hump is formed a first distance from the edge of the wafer, etching back the spin-on-glass layer wherein the wafer is held by a clamp a second distance from the edge of the wafer wherein the second distance is smaller than the first distance and wherein the etching back of the spin-on-glass layer forms the polymer on the surface of the first oxide layer under the clamp at a third distance between the first and second distances, and depositing a second oxide layer overlying the etched back spin-on-glass layer and the polymer at the edge of the wafer to complete the interlevel dielectric sandwich layer.

Abstract: A plasma processing method of performing plasma processing such as plasma film formation processing on a target object arranged in a processing vessel is disclosed. This method includes the first step of introducing an inert gas into the processing vessel, the second step of generating a plasma of the inert gas in the processing vessel, the third step of introducing a processing gas for processing the target object into the processing vessel, and the fourth step of generating a plasma of the processing gas in the processing vessel to process the target object.

Abstract: A method for forming a high-performance oxide as a tunneling dielectric for non-volatile memory applications. A silicon film containing amorphous silicon and good crystalline silicon micrograins is deposited in a silicon substrate by a LPCVD system. Then, a oxidation is performed at a temperature selected in a range such that non-uniform epitaxial silicon growth occurs at the silicon substrate. During an initial thermal oxidation process, the amorphous silicon region is quickly oxidized to form SiO.sub.2 and the good-crystalline silicon micrograins are also quickly oxidized to form the silicon-rich SiO.sub.2 (TOAS). In a following oxidation process, silicon precipitates are formed at the silicon-enriched region and the non-uniform epitaxial silicon growth is also enhanced at the silicon-enriched region. The enhanced non-uniformed silicon growth creates mild microtips. The silicon precipitates connect to the mild silicon microtips.

Abstract: A method of producing hydrogenated amorphous silicon on a substrate by flowing a stream of safe (diluted to less than 1%) silane gas past a heated filament.

Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.

Abstract: A microcavity structure and a method for forming an integrated circuit device including a microcavity structure is disclosed. This invention includes a layer or substrate having a topography such as a pair of raised features. A void forming material, such as a Boro-Phosphorus Silicate Glass (BPSG) is deposited on the substrate such that a void is formed therein. A pinning material having a relatively greater density than the void forming material is deposited over the void forming material. The materials are then annealed by a process such as Rapid Thermal Anneal (RTA). The materials are then polished, by for example, Chemical Mechanical Polishing (CMP) to expose the top of the void. The void is then etched using an anisotropic etch, such as Reactive Ion Etch (RIE) to remove the void forming material. The method may be used to provide self-aligned contact vias.

Abstract: A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate glass structure is formed by depositing at least two alternating layers of heavily-doped silicate glass and lightly-doped silicate glass over the first layer. Both the heavily-doped silicate glass and lightly-doped silicate glass layers may comprise glass doped with both a first dopant and a second dopant. The first dopant may represent, for example, phosphorous, and the second dopant may represent, for example, boron.

Abstract: Organic films are applied from solvent solution to a substrate, then are ion implanted to have resistivity in the kilohm/square to gigaohm/square range. The films are then patterned by standard lithographic procedures, with surprisingly little loss of conductivity, in spite of contact with organic solvents or acidic or basic etchant solutions during the patterning process. Both structures which contact the substrate, and freestanding conductive polymer bridges, can be formed. The invention provides a method of producing electrical devices which does not require the use of single crystal semiconductor substrates or deposition of inorganic semiconductors. The resulting devices are highly resistant to damage from abrasion, solvents, acids, bases, and moisture.

Abstract: A silicon carbide substrate is dry-polished using chromium oxide Cr.sub.2 O.sub.3, ion oxide Fe.sub.2 O.sub.3, or cerium oxide CeO.sub.2 to obtain a good polished surface free of mechanical defects and with less crystal distortion. Films are then formed on the surface to create an improved electronic device.

Abstract: A process for lowering the dielectric constant of a layer on a semiconductor wafer is described. The presence of the fullerene in the composite layer changes its dielectric constant. The process forms, on the wafer, a composite layer comprising matrix-forming material and a fullerene. The fullerene may be removed from the composite layer to leave an open porous layer. Removing the fullerene may be accomplished, for example, by contacting the composite layer with a liquid which is a solvent for the fullerene but not for the insulation material or by oxidizing the fullerene. The processes and insulation layers described are particularly useful for integrated circuits.

Abstract: The present invention relates to a method for forming a silicon dioxide layer on a silicon substrate, which is suitable for use as a thin-gate oxide. The method includes conducting an electrolytic reaction at a room temperature such that a silicon dioxide layer is formed on a silicon substrate acting as an anode, wherein pure water is used as an electrolyte of the electrolytic reaction. The silicon dioxide layer is further subjected with a rapid thermal densification carried out in an inert gas atmosphere and at a temperature of 700.degree.-1000.degree. C. for a period of time such that the silicon dioxide layer formed on said silicon substrate is densified.

Abstract: A method of producing a device having a minute structure such as a semiconductor element. The producing method comprises the following steps: (a) forming a film of liquid containing a sublimable material on a surface of a product of the device, the sublimable material being solid ordinary temperature and at normal pressure, the minute structure being formed at the surface of the product; (b) improving a wettability of at least one of the minute structure and a region surrounding the minute structure by the liquid film of the sublimable material; (c) converting the liquid film into a state containing the sublimable material in solid phase so as to form a protective film; and (d) vaporizing the protective film to be removed.