Abstract: A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A dispersed storage (DS) method begins by issuing a plurality of write commands to a plurality of DS storage units. The method continues by receiving a write acknowledgement from one of the plurality of DS storage units to produce a received write acknowledgement. The method continues by issuing a plurality of commit commands to the plurality of DS storage units when a write threshold number of the received write acknowledgements have been received. The method continues by receiving a commit acknowledgement from a DS storage unit of the plurality of DS storage units to produce a received commit acknowledgement. The method continues by issuing a plurality of finalize commands to the plurality of DS storage units when a write threshold number of the received commit acknowledgements have been received.

Abstract: A control apparatus connectable to a memory unit for storing data, for controlling a first tape writing unit including a plurality of first tapes and a second tape writing unit including a plurality of second tapes so that the first and second writing units write same data stored in the memory unit to one of the first tapes and one of the second tapes, respectively, has an obtaining unit for obtaining a progress value indicating a progress of writing data into the one of the second tapes upon completely writing the data into one of the first tapes and a controller for controlling the first and the second tape writing units so that the first and the second writing unit change the writing tapes to another of the first tapes and another of second tapes when the progress value being not more than a predetermined value.

Abstract: Embodiments of the present invention provide a hybrid RAID controller with multi PCI bus switching for a storage device of a PCI-Express (PCI-e) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a hybrid RAID controller having multiple (e.g., two or more) sets of RAID circuitry that are interconnected/coupled to on another via a PCI bus to enable real-time switching. Each set of RAID circuitry is coupled to a one or more (i.e., a set of) semiconductor storage device (SSD) memory disk units and/or HDD/Flash memory units.

Abstract: A system and method for managing multiple fingerprint tables in a deduplicating storage system. A computer system includes a storage medium, a first fingerprint table comprising a first plurality of entries, and a second fingerprint table comprising a second plurality of entries. Each of the first plurality of entries and the second plurality of entries are configured to store fingerprint related data corresponding to data stored in the storage medium. A storage controller is configured to select the first fingerprint table for storage of entries corresponding to data stored in the data storage medium that has been deemed more likely to be successfully deduplicated than other data stored in the data storage medium; and select the second fingerprint table for storage of entries corresponding to data stored in the data storage medium that has been deemed less likely to be successfully deduplicated than other data stored in the storage medium.

Abstract: Problem To recover data of a virtual volume to which an external volume was assigned even if an unusual status occurs in the first storage apparatus. Solution The controller of the storage apparatus, to the respective pages of the pool corresponding to the virtual volumes, assigns the internal pool volumes configured of storage devices of the storage apparatus or the external pool volumes configured of storage devices of the storage apparatus, and the management server stores the configuration information indicating the correspondence relationship between the external pool volumes assigned to the respective pages of the pool and the virtual volumes, in the case of a total functional shutdown of the storage apparatus, creates a virtual volume and a pool in the storage apparatus, associates the virtual volume with the external pool volume in accordance with the stored configuration information, provides the virtual volume to the host computer and instructs path switching.

Abstract: A computer includes an enclosure, an internal mass storage device within the enclosure, and a redundancy controller within the enclosure. At least one port enables direct connection of the computer to at least one external mass storage device. The redundancy controller is configured to provide data redundancy using the internal mass storage device and the at least one external storage device if the at least one external mass storage device is connected to the at least one port.

Abstract: This storage system supplies, to a plurality of computers, a plurality of duplicate volumes (CVOLs) (corresponding to duplicates of a master volume (MVOL) upon which is stored an electronic object (EO) that is common to the plurality of computers). Both the MVOL and the CVOLS are virtual logical volumes that follow sync provisioning. In the plurality of CVOLs, a plurality of physical regions that are allocated to the MVOL (i.e. regions in which the electronic object is stored) (PAs) are allocated. A storage, when writing an electronic module (EM) to which the EO is applied to the first CVOL, copies data within a first PA that is allocated to the virtual region (VA) that is the write destination to a second PA, writes the EM to the second PA, and moreover allocates the second PA to a VA of the write destination, instead of the first PA. And the storage allocates the second PA to a VA within the second CVOL corresponding to the VA of the write destination, instead of the PA that is allocated to that VA.

Abstract: Various embodiments for performing truncate operations in nonvolatile memory are described. In one embodiment, an apparatus may include a nonvolatile memory to perform one or more truncate operations on a data file written to the nonvolatile memory and a volatile memory to track a truncate operation performed in the nonvolatile memory. Other embodiments are described and claimed.

Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.

Abstract: A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.

Abstract: A memory card of one published standard, such as the Multi-Media Card (MMC) or Secure Digital Card (SD), is modified to include the function of a Subscriber Identity Module (SIM) according to another published standard. The controller of the memory card communicates between electrical contacts on the outside of the card and both the memory and the SIM. In one specific form, the memory card has the physical configuration of the current Plug-in SIM card with a few external contacts added to accommodate the memory controller and data memory. In another specific form, the memory card has the physical configuration of the current SD card, including external contacts.

Abstract: A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes.

Abstract: A system for booting an operating system from a virtual hard disk. A partitioned memory segment is formed within a memory by a preconfigured amount. A boot application is loaded into the partitioned memory segment to form a virtual hard disk. In response to determining that the virtual hard disk contains an operating system, the operating system is booted from the virtual hard disk.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.

Abstract: Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.

Abstract: The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

Abstract: In response to detecting a PCI host bridge (PHB), a first address translation table may be allocated in a first portion of a memory. The first address translation table may be associated with the PHB. If an input/output adapter accessible to the PHB is configured as a virtualized adapter, a first table manager may be assigned to manage the first address translation table. The first address translation table may be configured for an initial number of virtual functions. If a requested number of virtual functions is greater than the initial number of virtual functions, additional virtual functions may be configured. A second address translation table may be allocated in a second portion of the memory. The second portion of the memory may be non-contiguous with reference to the first portion of the memory. Entries may be created in the second address translation table for the additional virtual functions.