Patents Examined by Mehdi Namazi
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Patent number: 8782337Abstract: A storage system is described and includes a storage apparatus for storing data used by an external apparatus, first and second temporary data storage units, a host interface, a disk interface, and first and second controllers. The first controller is configured to select as a data transfer process, when the host interface receives a command from the external apparatus, one of a first data transfer process and a second data transfer process based on the command. The first data transfer process is a data transfer from the first temporary data storage unit to the external apparatus by the host interface. The second data transfer process is a data transfer from the first temporary data storage unit to the second temporary data storage unit by the second controller, and a data transfer from the second temporary data storage unit to the external apparatus by the host interface.Type: GrantFiled: October 17, 2012Date of Patent: July 15, 2014Assignee: Hitachi, Ltd.Inventors: Takeru Chiba, Sadahiro Sugimoto
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Patent number: 8751742Abstract: A method of extending memory card data storage capacity to a remote data store includes storing an initial data item received from a host device in a local memory cache, and wirelessly transmitting the initial data item from the local memory cache to the remote data store via a network interface that includes at least one wireless communication transceiver. The method also includes substituting a corresponding, smaller transcoded data item received from the remote data store for the initial data item in the local memory cache.Type: GrantFiled: April 1, 2011Date of Patent: June 10, 2014Assignee: Telefonaktiebolaget L M Ericsson (Publ)Inventor: Johannes Wilke
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Patent number: 8745318Abstract: Methods and systems involve collecting memory device parameters and using memory device parameters to determine memory wear information. A set of first parameters associated with wear of the memory device is monitored for at least one memory unit of the memory device. The first parameters are compared to respective trigger criterion. If the comparison reveals that one or more of the first parameters are beyond their trigger criterion, then collection of a second set of parameters is triggered. The second parameters are also indicative of the wear of the memory device. The set of first parameters may overlap the set of second parameters. The set of second parameters are used to develop memory wear information. In some implementations, the memory wear information may be configuration information used to configure the read/write channel to compensate for wear of the memory device. In some implementations, the memory wear information may be used to predict or estimate the lifetime of the device.Type: GrantFiled: June 28, 2011Date of Patent: June 3, 2014Assignee: Seagate Technology LLCInventors: Bernardo Rub, Ara Patapoutian, Bruce Buch
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Patent number: 8738846Abstract: A file system-aware SSD management system including an SSD management module that incorporates both file system information and information related to the underlying physical solid-state storage media into its operations is described. Also described are related methods for performing data management operations in a file system-aware manner. By incorporating both file system and physical storage information, the system may achieve various advantages over conventional systems, such as enhanced I/O performance, simplified SSD firmware, and extended SSD lifespan. Moreover, by moving solid-state management functions above the firmware level, the system may enable the simultaneous management of a pool of multiple SSDs.Type: GrantFiled: October 14, 2011Date of Patent: May 27, 2014Assignee: Arkologic LimitedInventors: Kyquang Son, Ronald Lee, Henry C. Lau, Rajesh Ananthanarayanan
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Patent number: 8732414Abstract: A control device including: a storage device that includes a first storage area including a plurality of blocks into which data can be written more than once and a second storage area into which data can be written only once, wherein the first storage area further stores a flag for each of the blocks, the flag indicating whether or not the block is allowed to be used; a flag management information creation unit configured to create, on the basis of the flag, a flag management information for managing whether or not data can be stored in each block of the storage device; and a management information controller configured to cause the flag management information to be stored in the second storage area.Type: GrantFiled: June 28, 2011Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventors: Yoko Kawano, Yuji Hanaoka, Atsushi Uchida
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Patent number: 8725964Abstract: A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.Type: GrantFiled: September 7, 2012Date of Patent: May 13, 2014Assignee: CommVault Systems, Inc.Inventors: Anand Prahlad, Randy DeMeno, Jeremy A. Schwartz, James J. McGuigan
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Patent number: 8725981Abstract: A storage system for storage of data written from a computer, and when a write request of data to a first logical volume is received, the data on request is stored into the first logical volume. When a first-generation snapshot creation request is received, the data stored in the first logical volume at the time of receiving the first-generation snapshot creation request is written into a pool region as data corresponding to a first-generation snapshot, and when a second-generation snapshot creation request is received, any portion of the data updated after the first-generation snapshot creation request is received but before the second-generation snapshot creation request is issued is read from the first logical volume for writing into the pool region. Such a storage system favorably implements snapshot backup with no dependency with a positive volume in terms of performance and failure, and with high capacity efficiency.Type: GrantFiled: October 31, 2012Date of Patent: May 13, 2014Assignee: Hitachi, LtdInventors: Yoshiaki Eguchi, Shunji Kawamura
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Patent number: 8719524Abstract: A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area.Type: GrantFiled: October 7, 2011Date of Patent: May 6, 2014Assignee: Hitachi, Ltd.Inventors: Tomohiro Yoshihara, Akira Deguchi, Hiroaki Akutsu
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Patent number: 8694712Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.Type: GrantFiled: December 5, 2006Date of Patent: April 8, 2014Assignee: Microsoft CorporationInventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 8694718Abstract: In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.Type: GrantFiled: December 30, 2008Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Massimo Iaculo, Ornella Vitale, Antonino Pollio
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Patent number: 8683156Abstract: Data blocks are copied from a source (e.g., a source virtual disk) to a target (e.g., a target virtual disk). The source virtual disk format is preserved on the target virtual disk. Offsets for extents stored in the target virtual disk are converted to offsets for corresponding extents in the source virtual disk. A map of the extents for the source virtual disk can therefore be used to create, for deduplication, segments of data that are aligned to boundaries of the extents in the target virtual disk.Type: GrantFiled: December 7, 2011Date of Patent: March 25, 2014Assignee: Symantec CorporationInventors: Ashutosh Kanhaiya Bahadure, Carl James Appellof, Edward Michael Goble
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Patent number: 8677054Abstract: A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.Type: GrantFiled: December 9, 2010Date of Patent: March 18, 2014Assignee: Apple Inc.Inventors: Avraham Meir, Oren Golov
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Patent number: 8677097Abstract: A method of configuring a computer memory system includes receiving a request from customized software driver or a BIOS extension software or a customized legacy BIOS or a customized UEFI PMM extension software or a customized UEFI BIOS, scanning memory module sockets in response to the request, recognizing memory modules in the memory module sockets, the memory modules being made of, at least in part, persistent memory modules (PMMs), configuring the PMMs to be invisible to the OS, and storing the mapping information to a designated protected persistent memory area, and presenting the PMMs as a persistent block storage to the OS.Type: GrantFiled: October 17, 2012Date of Patent: March 18, 2014Assignee: Avalance Technology, Inc.Inventors: Siamack Nemazie, Ngon Van Le
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Patent number: 8671239Abstract: Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.Type: GrantFiled: December 8, 2010Date of Patent: March 11, 2014Assignee: SK Hynix Inc.Inventors: Wun Mo Yang, Yi Chun Liu
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Patent number: 8661191Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.Type: GrantFiled: January 26, 2012Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Patent number: 8656116Abstract: A shared memory made on a chip based on semiconductors comprising: an integer number m, greater than one, of data buses; m address and control buses; m input/output interfaces, each input/output interface being connected to one of the m data buses and to one of the m address and control buses; an integer number p, greater than one, of memory banks, each memory bank comprising: a memory, comprising a data input/output and an address and control input controlled by each of the address and control buses; a block of m switches, each of the m switches being connected on the one hand to a memory data bus, said memory data bus being connected to the data input/output of the memory, and on the other hand to one of the m data buses.Type: GrantFiled: August 14, 2008Date of Patent: February 18, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventor: Michel Harrand
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Patent number: 8656086Abstract: A background scheduler is provided that utilizes low-level communications (e.g., communications with a generic or controller-specific solid state, non-volatile memory driver) to control locking, reading, rewriting and unlocking of pages of data in the non-volatile memory. Such low-level communications cause data to be rewritten to the non-volatile memory independent of the file system in an effort to avoid data loss prior to an estimated data retention period.Type: GrantFiled: December 8, 2010Date of Patent: February 18, 2014Assignee: Avocent CorporationInventors: Arnaldo Zimmermann, James Imoto, Livio Ceci
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Patent number: 8650379Abstract: A data processing method for a nonvolatile memory system is described. In the method, a host CPU calls N data file segments, generates logical addresses, and then transfers the N data file segments and logical addresses to an ASIC. The ASIC then maps the logical addresses onto physical addresses of a nonvolatile memory, derives N payload data segments, and collectively generates corresponding metadata for all of the N payload data segments. Then, a single multi-segment transfer operation is performed to sequentially write the N payload data segments to a data block in the nonvolatile memory, and thereafter, write the corresponding metadata to a metadata block associated with the data block.Type: GrantFiled: December 7, 2011Date of Patent: February 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jung Woong Yang
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Patent number: 8645649Abstract: A computer system includes: a first storage apparatus; a second storage apparatus; a first volume of the first storage apparatus; and a second volume of the second storage apparatus; wherein the first volume and the second volume have a copy pair relationship and a host system recognizes the second volume as the same volume as the first volume; and wherein the first storage apparatus sends reservation information of the first volume to the second storage apparatus; and the second storage apparatus controls access from the host system on the basis of the received reservation information.Type: GrantFiled: September 29, 2011Date of Patent: February 4, 2014Assignee: Hitachi, Ltd.Inventors: Keiichi Kaiya, Noboru Furuumi, Kenta Ninose
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Patent number: 8612687Abstract: A mechanism is provided within a 3D stacked memory organization to spread or stripe cache lines across multiple layers. In an example organization, a 128B cache line takes eight cycles on a 16B-wide bus. Each layer may provide 32B. The first layer uses the first two of the eight transfer cycles to send the first 32B. The next layer sends the next 32B using the next two cycles of the eight transfer cycles, and so forth. The mechanism provides a uniform memory access.Type: GrantFiled: May 26, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Jian Li, William E. Speight, Lixin Zhang