Patents Examined by Mehdi Namazi
  • Patent number: 9311228
    Abstract: A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: David M. Daly, Tejas Karkhanis, Valentina Salapura
  • Patent number: 9304710
    Abstract: A storage system is described and includes a storage apparatus for storing data used by an external apparatus, first and second temporary data storage units, a host interface, a disk interface, and first and second controllers. The first controller is configured to select as a data transfer process, when the host interface receives a command from the external apparatus, one of a first data transfer process and a second data transfer process based on the command. The first data transfer process is a data transfer from the first temporary data storage unit to the external apparatus by the host interface. The second data transfer process is a data transfer from the first temporary data storage unit to the second temporary data storage unit by the second controller, and a data transfer from the second temporary data storage unit to the external apparatus by the host interface.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: April 5, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Takeru Chiba, Sadahiro Sugimoto
  • Patent number: 9299455
    Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: March 29, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Takashi Tsunehiro
  • Patent number: 9292228
    Abstract: A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: March 22, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Anant Baderdinni, Horia Simionescu, Luca Bert
  • Patent number: 9280470
    Abstract: An information processing system and computer program storage product for managing objects stored in a shared memory cache. The system includes at least a plurality of cache readers accessing data from the shared memory cache. The system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventor: Arun Iyengar
  • Patent number: 9280299
    Abstract: A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 8, 2016
    Assignee: Apple Inc.
    Inventors: Avraham Meir, Oren Golov
  • Patent number: 9274963
    Abstract: A method for managing objects stored in a shared memory cache. The method includes accessing data from the shared memory cache using at least a plurality of cache readers. A system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventor: Arun Iyengar
  • Patent number: 9256562
    Abstract: Machine implemented method and system are provided. A processor for a computing device allocates an address range with an address to write to an intermediate storage location. The processor configures a device communicating with the computing device for writing information at the intermediate storage location and at a plurality of storage locations. The computing device sends the address for the intermediate storage location with data that needs to be written at one of the plurality of storage locations with an identifier identifying the one of the plurality of storage locations; and the device first writes the data at the intermediate storage location and then updates the one of the plurality of storage locations identified by the identifier.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: February 9, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Kanoj Sarcar, Madhusudhan Harigovindan Thekkeettil
  • Patent number: 9251067
    Abstract: A device may comprise a plurality of non-volatile memories configured to store a plurality of physical pages and a controller coupled thereto, configured to program and read data to and from the plurality of non-volatile memory devices. The data may be stored in a plurality of logical pages (L-Pages) of non-zero length at starting addresses within the plurality of physical pages and execute first and second commands to indicate that first and second physical locations within the plurality of non-volatile memory devices no longer contains valid data and are now free space. This may be done by carrying out first and second virtual write operations of first and second L-Pages of a predetermined length at first and second unique addresses within a virtual address range that does not correspond to any of the physical pages, and accounting for an amount of free space gained as a result of executing the commands.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: February 2, 2016
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Andrew J. Tomlin
  • Patent number: 9244860
    Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 26, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Mark Gaertner, Mark Alan Heath
  • Patent number: 9229657
    Abstract: Accesses to a number of data blocks stored in a distributed storage are observed. Following observation of the accesses, the stored data blocks are redistributed. In one aspect, redistribution of the data blocks includes determining the access patterns for one or more of the data blocks based on the observed accesses, and determining the storage sizes for the one or more data blocks. Thereafter, based on the determined access patterns and determined storage sizes, the one or more data blocks are sorted. Subsequently, the one or more data blocks are redistributed or rebalanced across a number of storage devices of the distributed storage based on the sorting. In one aspect, the one or more data blocks are redistributed according to either a uniform distribution scheme or a proportional distribution scheme.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 5, 2016
    Assignee: Quantcast Corporation
    Inventors: Silvius V. Rus, Michael Ovsiannikov
  • Patent number: 9213631
    Abstract: A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: December 15, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Patent number: 9213864
    Abstract: A data processing apparatus includes an auxiliary storage device having target verification data stored therein, a program memory having a validity verification program stored therein, a first RAM (Random Access Memory), a second RAM, and an execution unit configured to execute a validity verification process in accordance with the validity verification program stored in the program memory. The execution unit is configured to copy the target verification data from the auxiliary storage device into the first RAM, execute the validity verification process on the copied target verification data in the first RAM, and use the second RAM as a work area in a case of executing the validity verification process.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: December 15, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventor: Kei Kato
  • Patent number: 9208025
    Abstract: A method for evolving dispersed storage network (DSN) memory in a DSN begins by a processing module generating tracking information by tracking evolutionary change of storage units of the DSN memory, performance and reliability requirements of the DSN memory, and memory utilization of the DSN memory. The method continues with the processing module, for a given state of evolution of the DSN memory, interpreting the tracking information to produce given state DSN memory data and establishing virtual DSN address boundaries for a set of the storage units for storing data objects in a virtual memory vault of the DSN, where the virtual memory vault is mapped to the set of the storage units, where the data objects are dispersed storage error encoded into pluralities of sets of encoded data slices that are stored in the set of the storage units in accordance with the virtual DSN address boundaries.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: December 8, 2015
    Assignee: CLEVERSAFE, INC.
    Inventors: Greg Dhuse, Andrew Baptist
  • Patent number: 9207870
    Abstract: A method begins by a processing module detecting a new storage unit within a dispersed storage network DSN. The method continues with the processing module determining to affiliate the new storage unit with a virtual memory vault, where the virtual memory vault is mapped to a set of storage units of the DSN, where data objects are dispersed storage error encoded into pluralities of sets of encoded data slices that are stored in the set of storage units. The method continues with the processing module determining virtual DSN addresses of the virtual memory vault to allocate the new storage unit. The method continues with the processing module updating vault information regarding the virtual memory vault to include the allocation of the virtual DSN addresses to the new storage unit.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: December 8, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Andrew Baptist, Greg Dhuse
  • Patent number: 9201779
    Abstract: A management system manages a computer system having multiple storage apparatuses, which provide a virtual volume to a host. The computer system includes a pool, and the storage apparatus allocates a physical page in the pool to a write destination when writing to the virtual volume. The management system stores logical volume management information for managing a corresponding relationship between a storage apparatus in which a logical volume resides and a physical page forming the logical volume, and virtual volume management information for managing the corresponding relationship between a virtual segment in a virtual volume and a page allocated to the virtual segment, and based on the logical volume management information and the virtual volume management information identifies a first page migration, which is affected in a case where either a determination-target storage apparatus is stopped or a first storage area is blocked, and displays the first page migration information.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 1, 2015
    Assignee: HITACHI, LTD.
    Inventors: Yoshitaka Tokusho, Yuuki Miyamoto
  • Patent number: 9201677
    Abstract: Systems and methods for managing data input/output operations are described that include virtual machines operating with a shared storage within a host. In such a system, a computer-implemented method is provided for dynamically provisioning cache storage while operating system applications continue to operate, including stalling the virtual machine's local cache storage operations, changing the provision of cache storage size; and resuming the operations of the virtual machine.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 1, 2015
    Assignee: Intelligent Intellectual Property Holdings 2 LLC
    Inventors: Vikram Joshi, Yang Luan, Manish R. Apte, Hrishikesh A. Vidwans, Michael F. Brown
  • Patent number: 9189390
    Abstract: In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Massimo Iaculo, Ornella Vitale, Antonino Pollio
  • Patent number: 9164911
    Abstract: A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Jonathan T. Hsieh, Christian Jacobi, Timothy J. Slegel
  • Patent number: 9152562
    Abstract: Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 6, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Randhir Thakur, Christopher Moore