Patents Examined by Mehdi Namazi
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Patent number: 8327108Abstract: An electronic slave device includes a hardware data packing block having a configurable multiplexing unit having inputs connected to system bus, wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; a format register, the value of which can be set by an external master device to at least two different values; and a logic circuit capable of setting the connections of the multiplexing unit according to the value of the format register to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.Type: GrantFiled: October 20, 2006Date of Patent: December 4, 2012Assignee: ST-Ericsson SAInventors: Daineche Layachi, Emmanuel Alie, Laurent Capella
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Patent number: 8327058Abstract: Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.Type: GrantFiled: July 25, 2008Date of Patent: December 4, 2012Assignee: Broadcom CorporationInventors: Tak (Tony) Lee, Bazhong Shen
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Patent number: 8316203Abstract: A storage system for storage of data written from a computer, and when a write request of data to a first logical volume is received, the data on request is stored into the first logical volume. When a first-generation snapshot creation request is received, the data stored in the first logical volume at the time of receiving the first-generation snapshot creation request is written into a pool region as data corresponding to a first-generation snapshot, and when a second-generation snapshot creation request is received, any portion of the data updated after the first-generation snapshot creation request is received but before the second-generation snapshot creation request is issued is read from the first logical volume for writing into the pool region. Such a storage system favorably implements snapshot backup with no dependency with a positive volume in terms of performance and failure, and with high capacity efficiency.Type: GrantFiled: January 13, 2009Date of Patent: November 20, 2012Assignee: Hitachi, Ltd.Inventors: Yoshiaki Eguchi, Shunji Kawamura
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Patent number: 8316195Abstract: One embodiment provides a storage system and a data transfer method of a storage system, and particularly a storage system and a data transfer method of a storage system that can achieve higher data I/O performance even when hardware resources are limited.Type: GrantFiled: September 10, 2010Date of Patent: November 20, 2012Assignee: Hitachi, Ltd.Inventors: Takeru Chiba, Sadahiro Sugimoto
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Patent number: 8301860Abstract: Mechanisms are provided for detecting changes in virtual storage device configurations. The mechanisms detect an event corresponding to a change in configuration of a virtual storage device. The virtual storage device is comprised of a plurality of portions of a plurality of physical storage devices. The mechanisms further, in response to detecting the event, determine if the change in configuration of the virtual storage device results in a change in the types of physical storage devices that are part of the virtual storage device. Moreover, the mechanisms further transmit a notification, in response to a determination that the change in configuration of the virtual storage device results in a change in the types of physical storage devices that are part of the virtual storage device, of the results of the change in configuration of the virtual storage device to one or more registered recipients registered to receive such notifications.Type: GrantFiled: October 16, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Michael P. Cyr, James A. Pafumi, Jacob J. Rosales, Morgan J. Rosas
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Patent number: 8296540Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: February 25, 2008Date of Patent: October 23, 2012Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 8296514Abstract: Systems and methods for managing storage virtualization in a storage infrastructure are provided. The method comprises examining storage virtualization configurations across a data storage infrastructure having one or more data storage resources, such that configuration data associated with the storage virtualization configurations applied to the one or more data storage resources is stored in a configuration repository; analyzing the configuration data to detect storage virtualization policy inconsistencies across the data storage infrastructure; reporting potential problems associated with applying the storage virtualization configurations to said one or more data storage resources; and automatically implementing recommendations for corrective action to improve storage virtualization, in response to detecting the virtualization policy inconsistencies.Type: GrantFiled: December 20, 2007Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: David Gregory Van Hise, Gregory John Tevis
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Patent number: 8281094Abstract: When performing asynchronous remote copying, whether or not a disaster has occurred at a main site is judged at a remote site; and if the disaster has occurred, recovery processing is immediately started at the remote site. When asynchronous remote copying is performed between a controller and a controller, the controller transfers remote copy target data in a storage apparatus and command information via a remote copy channel to the controller; and after receiving the remote copy target data, the controller stores the remote copy target data in a storage apparatus; and if the controller fails to receive the command information within a set time period, the controller judges that a disaster has occurred, and then outputs the judgment result to a backup center server; and the backup center server executes recovery processing based on data in the storage apparatus when the disaster has occurred.Type: GrantFiled: August 26, 2009Date of Patent: October 2, 2012Assignee: Hitachi, Ltd.Inventors: Yoshifumi Miyatake, Takuya Ichikawa, Katsuhiro Okumoto
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Patent number: 8275966Abstract: A dispersed storage device within a dispersed storage network includes a processing module for determining whether to add a new generation for a vault, in which the vault identifies at least one user having data to be stored. When the new generation is to be added to the vault, the processing module further assigns a vault generation identifier to the new generation, assigns a virtual address range of a virtual memory associated with the dispersed storage network to the new generation and maps the virtual address range to a physical memory for storage of the data therein.Type: GrantFiled: April 21, 2010Date of Patent: September 25, 2012Assignee: Cleversafe, Inc.Inventors: Andrew Baptist, Greg Dhuse
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Patent number: 8275927Abstract: Methods and apparatus are provided for a solid state non-volatile storage sub-system of a computer. The storage sub-system includes a write-once storage sub-system memory device and a write-many storage sub-system memory device. The write-once storage sub-system memory device includes a recoverable system configuration. Numerous other aspects are provided.Type: GrantFiled: December 31, 2007Date of Patent: September 25, 2012Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Randhir Thakur, Christopher Moore
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Patent number: 8271754Abstract: A system, method and computer-usable medium are disclosed for recovering data from a memory storage device. The operating system (OS) of an IPS comprising a source memory storage device, further comprising stored data, is monitored to detect a defective operating state. If a defective operating state of the OS is detected, then operation of the IPS is terminated, followed by the initiation of IPS boot operations to recover data from the source memory storage device. The OS is bypassed, and initial boot operations are performed from a management controller or from the BIOS of the IPS. Additional boot operations are performed, and once the IPS has been brought to an operative state, a data recovery module is used to transfer data from the source memory storage device to a target storage device.Type: GrantFiled: October 5, 2009Date of Patent: September 18, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Terry L. Cole, Paul W. Vancil
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Patent number: 8271735Abstract: A new “held” (“H”) cache-coherency state is introduced for directory-based multiprocessor systems. Using the held state enables embodiments of the present invention to track sharers that have a shared copy of a cache line after a directory runs out of space for holding information that identifies processors that have received shared copies of the cache line (e.g., pointers to sharers of the cache line). In these embodiments, when a directory entry is full, the system provides subsequent shared copies of the cache line to sharers in the held state and tracks the identity of the held-copy owners in a data field in the entry for the cache line in a home node.Type: GrantFiled: January 13, 2009Date of Patent: September 18, 2012Assignee: Oracle America, Inc.Inventor: Robert E. Cypher
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Patent number: 8271741Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.Type: GrantFiled: November 5, 2008Date of Patent: September 18, 2012Assignee: Microsoft CorporationInventors: Onur Mutlu, Thomas Moscibroda
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Patent number: 8266377Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.Type: GrantFiled: December 22, 2011Date of Patent: September 11, 2012Assignee: Hitachi, Ltd.Inventors: Yuri Hiraiwa, Nobuhiro Maki, Takeyuki Imazu
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Patent number: 8266397Abstract: A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.Type: GrantFiled: December 16, 2011Date of Patent: September 11, 2012Assignee: CommVault Systems, Inc.Inventors: Anand Prahlad, Randy DeMeno, Jeremy A. Schwartz, James J. McGuigan
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Patent number: 8261013Abstract: A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well.Type: GrantFiled: November 26, 2007Date of Patent: September 4, 2012Assignee: Hyperstone GmbHInventor: Franz Schmidberger
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Patent number: 8261021Abstract: In order to control an access request to the cache shared between a plurality of threads, a storage unit for storing a flag provided in association with each of the threads is included. If the threads enter the execution of an atomic instruction, a defined value is written to the flags stored in the storage unit. Furthermore, if the atomic instruction is completed, a defined value different from the above defined value is written, thereby displaying whether or not the threads are executing the atomic instruction. If an access request is issued from a certain thread, it is judged whether or not a thread different from the certain thread is executing the atomic instruction by referencing the flag values in the storage unit. If it is judged that another thread is executing the atomic instruction, the access request is kept standby. This makes it possible to realize the exclusive control processing necessary for processing the atomic instruction according to simple configuration.Type: GrantFiled: December 17, 2009Date of Patent: September 4, 2012Assignee: Fujitsu LimitedInventor: Naohiro Kiyota
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Patent number: 8261038Abstract: A method is provided method for allocating storage space. The method includes obtaining performance parameters for a storage pool, wherein the performance parameters comprise a size of the storage pool and a type of the storage pool. Proposed back end logical units (BELUs) to match the performance parameters are determined. Current disk groups for the proposed BELUs are identified, and if none exists, a plurality of storage arrays is analyzed to locate free disks that can be formed into a proposed disk group to support the creation of the proposed BELUs. A proposal is created showing the changes that would be made to a storage system to create the storage pool.Type: GrantFiled: April 22, 2010Date of Patent: September 4, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Marcus Vinicius Duarte Breda, Diogo Cesa Rosa, Timothy L. Virgo, Richelle L. Ahlvers-Dolphin, Diego Paprocki Abrianos, Marcelo Gomes De Oliveira, Rodrigo Menezes Do Prado, Alvaro De Vit Lunardi, Lucas Holz Boffo
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Patent number: 8255627Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.Type: GrantFiled: October 10, 2009Date of Patent: August 28, 2012Assignee: International Business Machines CorporationInventors: Stephen LaRoux Blinick, Cheng-Chung Song, Lokesh Mohan Gupta, Yu-Cheng Hsu
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Patent number: 8255631Abstract: A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.Type: GrantFiled: February 1, 2008Date of Patent: August 28, 2012Assignee: International Business Machines CorporationInventors: Lei Chen, Lixin Zhang