Abstract: A storage apparatus of an embodiment of the invention including one or more storage drives for providing real storage resources and a controller for controlling the one or more storage drives and accesses from a host computer. The controller initializes real storage resources and manages the initialized real storage resources. The controller receives an instruction for allocating an initialized real storage resource to a first virtual storage resource accessed by the host computer. In response to the instruction, the controller allocates a first initialized real storage resource which has been initialized in advance prior to the instruction to the first virtual storage resource.

Abstract: A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being placed into any of three or more physical states. An encoder is connected to receive data bits for storage and to apply activation signals to the row and column conductors to write information to the storage cells. The encoder is programmed to encode the data bits into entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; select entries in the array according to half-select currents of the storage cells; apply a predetermined one-dimensional mapping that increases the value of at most one entry in the array to obtain a mapped array; and write entries of the mapped array into the storage cells.

Abstract: One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.

Abstract: Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.

Abstract: A storage device and method for selective data compression are provided. In one embodiment, a storage device determines whether data stored in a storage area in the storage device's memory is suitable for compression. If the data is suitable for compression, the storage device compresses the data. The storage device then uses free memory space resulting from compressing the data for an internal storage device operation. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: A method of operation of a storage control system including: providing a memory controller; accessing a volatile memory table by the memory controller; writing a non-volatile semiconductor memory for persisting changes in the volatile memory table; and restoring a logical-to-physical table in the volatile memory table, after a power cycle, by restoring a random access memory with a logical-to-physical partition from a most recently used list.

Abstract: A dispersed storage device within a dispersed storage network includes a processing module for determining whether to add a new generation for a vault, in which the vault identifies at least one user having data to be stored. When the new generation is to be added to the vault, the processing module further assigns a vault generation identifier to the new generation and reserves memory for the new generation.

Abstract: A memory system according to at least one example embodiment stores meta data in a cache register when the memory system enters a standby mode. Therefore, the memory system may reduce power consumption in the standby mode, and/or rapidly perform a mode switch.

Abstract: A storage apparatus includes storage devices of a plurality of types of varying performance, and a control unit which manages each of storage areas provided by the storage devices of the plurality of types by means of storage tiers of a plurality of different types, and assigns the storage areas in page units to a virtual volume from any of the storage tiers among the storage tiers of the plurality of types. If the data I/O request is received from the host, the control unit assigns storage areas in page units from the uppermost storage tier to the target areas of the virtual volume corresponding to the I/O request The control unit changes the page unit storage area assignment to predetermined areas of the virtual volume from an upper storage tier to a lower storage tier in accordance with the speed of processing of the data I/O request.

Abstract: Method and apparatus for application profiling in a multi-device data storage array. In accordance with various embodiments, a storage array is formed of independent data storage devices that form a fast pool and a slow pool of said devices, such as solid-state drives (SSDs) and hard disc drives (HDDs). A controller is adapted to migrate a distributed data set stored across a first plurality of the devices in the slow pool to a second plurality of said devices in the fast pool. The controller carries out the migration responsive to a hint that a selected application is about to be executed that utilizes the distributed data set, and responsive to a return on investment (ROI) determination that an estimated cost of said migration will be outweighed by an overall improved data transfer capacity of the storage array over a predetermined minimum payback period of time.

Abstract: A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).

Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.

Abstract: A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is arranged to route each address transfer and associated data transfer via a first interface when the specified memory address is within a first memory address range, or to route each address transfer and associated data transfer via a second interface when the specified memory address is within a second memory address range and is further configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing.

Abstract: In an exemplary storage system, a processor assigns an unused process to a read request designating an area of a logical volume. The processor determines whether the data designated by the read request is in a cache memory, based on a first identifier for identifying the area designated by the read request. When the designated data is not in the cache memory and a part of physical volumes providing the logical volume is a first kind of physical volume, the processor stores the first identifier associated with an identifier for identifying an area allocated in the cache memory. When the designated data is not in the cache memory and a part of the physical volumes is a second kind of physical volume, the processor stores a second identifier for identifying the process assigned to the read request associated with an identifier for identifying an area allocated in the cache memory.

Abstract: A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period.

Abstract: A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.

Abstract: A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

Abstract: An indexing method is based on a tree structure of a flash memory, which includes a plurality of pages. The indexing method stores an entry in the leaf node and an entry in an index node designating the leaf node, in the same page, and changes the maximum number of entries that are stored in the leaf node of the page and the maximum number of entries that are stored in the index node of the page on the basis of the number of entries in the leaf node and the number of entries in the index node, respectively.

Abstract: An information processing apparatus includes a volatile main storage; a nonvolatile first-auxiliary storage; a nonvolatile second-auxiliary storage for storing second data; a processing unit for loading the second data from the second-auxiliary storage into the main storage; a storing unit for storing first data stored in the main storage into the first-auxiliary storage at a predetermined timing, wherein the first data includes the second data that was loaded into the main storage from the second-auxiliary storage; and a loading unit for loading the first data stored in the first-auxiliary storage into the main storage. After the loading unit loads the first data into the main storage, the processing unit loads, from the second-auxiliary storage into the main storage, the second data that was changed after the storing unit stored the first data into the first-auxiliary storage from the main storage section.

Abstract: Method and apparatus for managing data in a multi-device data storage array. In accordance with various embodiments, a storage array of independent data storage devices are arranged to form a fast pool and a slow pool of said devices. A controller is adapted to migrate a distributed data set stored across a first plurality of said devices in the slow pool to a second plurality of said devices in the fast pool. The migration is carried out responsive to a return on investment (ROI) determination by the controller that an estimated cost of said migration will be outweighed by an overall improved data transfer capacity of the storage array over a predetermined minimum payback period of time. In some embodiments, the fast pool is formed from a plurality of solid-state drives (SSDs) and the slow pool is formed from a plurality of hard disc drives (HDD).