Patents Examined by Mehdi Namazi
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Patent number: 9891830Abstract: A hierarchal storage management method is provided. The method includes detecting a first portion of a first file being deleted from a hybrid storage device including a hard disk drive (HDD) memory device, a solid state drive (SSD) memory device, and an archival storage memory device. A first set of memory blocks associated with the first portion of the first file is identified. The first set of memory blocks are determined to reside on the SSD memory device. In response, the first set of memory blocks are transferred from the SSD memory device to a first portion of the hybrid storage device.Type: GrantFiled: April 5, 2017Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Blaine H. Dolph, Nataraj Nagaratnam, Sandeep R. Patil, Riyazahamad M. Shiraguppi
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Patent number: 9891865Abstract: A method of providing special functions includes receiving from a host a first normal command and a first address, and identifying a first special function based on the first normal command and the first address when the first address is in an address range established for special functions according to a predefined rule.Type: GrantFiled: February 23, 2015Date of Patent: February 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventor: Joon-Ho Lee
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Patent number: 9881099Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.Type: GrantFiled: May 24, 2010Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Danie M. Dreps, Luis A Lastras-Montano, Michael J Shapiro
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Patent number: 9880930Abstract: A method of operating a controller includes receiving write data having chunks from a host, assigning each of finger prints to each of the chunks, counting the number of duplications of each of the finger prints, and changing a physical address assigned to each of first finger prints among the finger prints based on a count value of each of the finger prints based on a count value of each of the finger prints, and the physical address is assigned by a flash translation layer (FTL).Type: GrantFiled: June 10, 2015Date of Patent: January 30, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Young Jin Park
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Patent number: 9870161Abstract: In order to ensure that a normally-off computer connected to a volatile component operates normally and rapidly after operation of turning-on/off of a power supply is executed, a computation processing device which has nonvolatile registers and which is able to continue processing of data retained in the device after the power supply is turned off/on without retracting the data to an external device includes at least: a central processing unit including the nonvolatile registers; a connection unit for a volatile component which saves internal information in a volatile storage element thereof; a nonvolatile storage unit for saving a return program from a power-off state of the volatile component; and an inspection unit notifying that a potential of the power supply in the computation processing device has reached an operation potential at a time of return.Type: GrantFiled: March 24, 2014Date of Patent: January 16, 2018Assignee: NEC CORPORATIONInventors: Yukihide Tsuji, Yukikazu Nakamoto
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Patent number: 9870315Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.Type: GrantFiled: January 27, 2017Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Jan Van Lunteren, Heiner Giefers
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Patent number: 9858182Abstract: A garbage collection method of a data storage system having storage devices is provided. The method includes determining whether a garbage collection is needed in one of the storage devices, transferring a multicast garbage collection command from one of the storage devices to at least one other storage device in a write group through a multicast operation, and performing the garbage collection in one of the storage devices.Type: GrantFiled: June 10, 2015Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wooseok Chang, Kangho Roh, Jongwon Lee
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Patent number: 9811551Abstract: A system and method for managing fingerprint tables in deduplicating storage systems. A computer system includes a storage device and a data storage controller coupled to the storage device. The controller is configured to for each of a plurality of data objects stored in a storage device, determine, based on one or more attributes corresponding to usage of the data object, a probability of the data object being deduplicated; store within a first fingerprint table, fingerprints of data objects with the highest probability of being deduplicated; store within a second fingerprint table, fingerprints of data objects with a lower probability of being deduplicated than the data objects having fingerprints stored in the first fingerprint table; and search fingerprints of the first fingerprint table to determine whether a fingerprint for a data object associated with a write request matches a fingerprint for any of the data objects in the first fingerprint table.Type: GrantFiled: June 25, 2015Date of Patent: November 7, 2017Assignee: Pure Storage, Inc.Inventors: John Colgrove, John Hayes, Ethan Miller, Joseph S. Hasbani, Cary Sandvig
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Patent number: 9811262Abstract: Accesses to a number of data blocks stored in a distributed storage are observed. Following observation of the accesses, the stored data blocks are redistributed. In one aspect, redistribution of the data blocks includes determining the access patterns for one or more of the data blocks based on the observed accesses, and determining the storage sizes for the one or more data blocks. Thereafter, based on the determined access patterns and determined storage sizes, the one or more data blocks are sorted. Subsequently, the one or more data blocks are redistributed or rebalanced across a number of storage devices of the distributed storage based on the sorting. In one aspect, the one or more data blocks are redistributed according to either a uniform distribution scheme or a proportional distribution scheme.Type: GrantFiled: November 21, 2016Date of Patent: November 7, 2017Inventors: Silvius V. Rus, Michael Ovsiannikov
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Patent number: 9804970Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.Type: GrantFiled: September 27, 2016Date of Patent: October 31, 2017Assignee: International Business Machines CorporationInventors: Timothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck
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Patent number: 9798661Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.Type: GrantFiled: October 15, 2013Date of Patent: October 24, 2017Assignee: HITACHI, LTD.Inventors: Yoshifumi Mimata, Yuko Matsui, Shintaro Kudo
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Patent number: 9792067Abstract: A device may comprise a plurality of non-volatile memory devices configured to store a plurality of physical pages and a controller coupled thereto, configured to program and read data to and from the plurality of non-volatile memory devices. The data may be stored in a plurality of logical pages (L-Pages) of non-zero length at starting addresses within the plurality of physical pages. The controller may be configured to execute first and second commands to indicate that first and second physical locations within the plurality of non-volatile memory devices no longer contain valid data and are now free space. This may be done by carrying out first and second virtual write operations of first and second L-Pages of a predetermined length at first and second unique addresses within a virtual address range that does not correspond to any of the physical pages, and accounting for an amount of free space gained as a result of executing the commands.Type: GrantFiled: January 7, 2016Date of Patent: October 17, 2017Assignee: Western Digital Technologies, Inc.Inventor: Andrew J. Tomlin
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Patent number: 9753644Abstract: A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.Type: GrantFiled: January 27, 2014Date of Patent: September 5, 2017Assignee: Apple Inc.Inventors: Avraham Meir, Oren Golov
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Patent number: 9747216Abstract: A computer processor including a first memory structure that operates over multiple cycles to temporarily store operands referenced by at least one instruction. A plurality of functional units performs operations that produce and access operands stored in the first memory structure. A second memory structure is provided, separate from the first memory structure. The second memory structure is configured as a dedicated memory for storage of operands copied from the first memory structure. The second memory structure is organized with a byte-addressable memory space and each operand stored in the second memory structure is accessed by a given byte address into the byte-addressable memory space.Type: GrantFiled: June 23, 2014Date of Patent: August 29, 2017Assignee: Mill Computing, Inc.Inventors: Roger Rawson Godard, Arthur David Kahlich, Sebastien Paul Maurice Mirolo, David Arthur Yost
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Patent number: 9734014Abstract: A method for generating virtual dispersed storage network (DSN) addresses includes dispersed storage error encoding a data segment of a data object to produce a set of encoded data slices of a plurality of sets of encoded data slices of the pluralities of sets of encoded data slices. The method further includes generating, for each encoded data slice of the set of encoded data slices, a virtual DSN address having a slice name that includes a vault identifier, a slice index, a data object identifier, and a data segment identifier. The method further includes obtaining a mapping of a vault to a set of storage units of the DSN, wherein the mapping indicates how the set of encoded data slices are to be stored. The method further includes outputting the set of encoded data slices to the set of storage units in accordance with the mapping.Type: GrantFiled: November 2, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Greg Dhuse, Andrew Baptist
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Patent number: 9734056Abstract: A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration management unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches.Type: GrantFiled: November 13, 2013Date of Patent: August 15, 2017Assignee: Southeast UniversityInventors: Longxing Shi, Jun Yang, Peng Cao, Bo Liu, Jinjiang Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
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Patent number: 9727255Abstract: A storage apparatus includes a semiconductor storage device, and a storage controller coupled to the semiconductor storage device, and which stores data to a logical storage area provided by the semiconductor storage device. The semiconductor storage device includes one or more non-volatile semiconductor storage media, and a medium controller coupled to the semiconductor storage media. The medium controller compresses data stored in the logical storage area, and stores the compressed data in the semiconductor storage medium. The size of a logical address space of the logical storage area is larger than a total of the sizes of physical address spaces of the semiconductor storage media.Type: GrantFiled: July 19, 2013Date of Patent: August 8, 2017Assignee: Hitachi, Ltd.Inventor: Takaki Matsushita
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Patent number: 9727469Abstract: According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.Type: GrantFiled: February 15, 2013Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
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Patent number: 9704574Abstract: Aspects of the disclosure provide an apparatus that includes a key generator, a first memory, a second memory, and a controller. The key generator is configured to generate a first search key, and one or more second search keys in response to a pattern. The first memory is configured to compare the first search key to a plurality of entries populated in the first memory, and determine an index of a matching entry to the first search key. The second memory is configured to respectively retrieve one or more exact match indexes of the one or more second search keys from one or more exact match pattern groups populated in the second memory. The controller is configured to select a search result for the pattern from among the index output from the first memory and the one or more exact match indexes output from the second memory.Type: GrantFiled: July 15, 2014Date of Patent: July 11, 2017Assignee: Marvell International Ltd.Inventor: Michael Shamis
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Patent number: 9690500Abstract: For efficient FlashCopy backup target volume allocation, a target volume is dynamically allocated for a new FlashCopy backup by reusing an existing FlashCopy target volume containing older FlashCopy backups that have been previously ingested into a repository and are not currently being used as a source for at least one of a mount task, a clone task, and a restore task.Type: GrantFiled: April 2, 2014Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph W. Dain, Gregory T. Kishi, Osnat Shasha, Christopher Zaremba