Patents Examined by Metasebia T Retebo
  • Patent number: 11558051
    Abstract: An electronic power device including transistors formed on a circuit assembly formed of a plurality of layers. The layers include gate drive layers, gate return layers, and power layers. A gate drive circuit is formed on the circuit assembly, and is connected to the gate and source of each of the transistors through the gate drive layers and the gate return layers. A voltage supply connection is provided to each of the plurality of transistors interleaved through the power layers. The circuit assembly includes a multilayer circuit board and/or a multilayer ceramic substrate. The ceramic substrate includes the power layers and transistors. The gate drive and return layers and gate drive circuit may be formed within the ceramic substrate or the circuit board. The ceramic substrate may be located in a modular housing. The circuit board may be outside the modular housing or inside the modular housing.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 17, 2023
    Assignee: BAE Systems Controls Inc.
    Inventors: Nicholas A. Lemberg, Robert J. Vovos
  • Patent number: 11558048
    Abstract: A nanosecond pulser may include a plurality of switch modules, a transformer, and an output. Each of the plurality of switch modules may include one or more solid state switches. The transformer may include a core, at least one primary winding wound around at least a portion of the core, each of the plurality of switch modules may be coupled with the primary windings, and a plurality of secondary windings wound at least partially around a portion of the core. The output may output electrical pulses having a peak voltage greater than about 1 kilovolt and having a pulse width of less than about 1000 nanoseconds. The output may output electrical pulses having a peak voltage greater than about 5 kilovolts, a peak power greater than about 100 kilowatts, a pulse width between 10 nanoseconds and 1000 nanoseconds, a rise time less than about 50 nanoseconds, or some combination thereof.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: January 17, 2023
    Assignee: Eagle Harbor Technologies, Inc.
    Inventors: Kenneth E. Miller, Timothy Ziemba
  • Patent number: 11552629
    Abstract: A semiconductor device includes a first transistor that flows a current to a load, a current generation circuit that outputs a current corresponding to a power consumption of the first transistor, a temperature sensor, a resistor-capacitor network coupled between the current generation circuit and the temperature sensor and an overheat detection circuit coupled to a connection point of the current generation circuit and the resistor-capacitor network, wherein the resistor-capacitor network comprises a resistor and a capacitor corresponding to a thermal resistance and a thermal capacitance between the first transistor and the temperature sensor.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 10, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroki Nagatomi, Makoto Tanaka
  • Patent number: 11552628
    Abstract: An electrical switching system includes a constant-power controller and a switching device electrically coupled between a first node and a second node. The constant-power controller is configured to (a) generate a digital control signal to control the switching device, (b) control a duration of an active phase of the digital control signal at least partially based on a voltage across the switching device, and (c) control a peak value of the digital control signal to regulate a peak magnitude of current flowing through the switching device.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: January 10, 2023
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Pietro Filoramo, Benedetto Marco Marietta, Carmelo Francesco Maria Marchese, Angelo Genova
  • Patent number: 11539362
    Abstract: A radio frequency (RF) switch includes a first terminal, a second terminal, a series switch circuit, a shunt switch circuit, an inductor and a reference voltage terminal. An RF signal at the first terminal. The series switch circuit is coupled to the first terminal, the second terminal, and the shunt switch circuit. The shunt switch circuit includes a sub-switch circuit, a transistor coupled to the sub-switch circuit, and a compensation capacitor parallel-coupled to the transistor. The inductor is coupled to the shunt switch circuit and the reference voltage terminal. When the RF signal is operated in a first frequency band, the first transistor is turned on for the shunt switch circuit and the inductor to provide a first impedance. When the RF signal is operated in a second frequency band, the first transistor is turned off for the shunt switch circuit and the inductor to provide a second impedance.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: December 27, 2022
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Pei-Chuan Hsieh, Tsung-Han Lee
  • Patent number: 11533051
    Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A first transistor has a source and a gate coupled to first and second voltage nodes respectively. A second transistor has a source and a gate coupled to third and second voltage nodes respectively. A third transistor is coupled between the first and second transistors. A fourth transistor has a source coupled to the first voltage node and a gate coupled to a first output node between the second and third transistors. A fifth transistor has a source coupled to the third voltage node, a gate coupled to the gate of the fourth transistor and a drain coupled to a drain of the fourth transistor. A sixth transistor has a gate supplied with a voltage output from a second output node between the fourth and fifth transistors and a source coupled to the first voltage node.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 20, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Eriko Shigesawa, Akio Ogura
  • Patent number: 11528025
    Abstract: A driver circuit is provided. The driver circuit comprises a power transistor and a gate driver circuit arrangement. The driver circuit is integrated in a package. In addition, the driver circuit comprises a terminal for an external transistor. The external transistor and the power transistor are controlled by the gate driver circuit arrangement in a mutually corresponding manner.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Robert Illing, Christian Djelassi-Tscheck, Christof Glanzer
  • Patent number: 11522541
    Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 6, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Joi Okugi, Daisuke Katori, Satoru Suzuki, Satoshi Kamiya
  • Patent number: 11502681
    Abstract: A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: November 15, 2022
    Assignee: Rambus Inc.
    Inventors: Talip Ucar, Frederick A. Ware
  • Patent number: 11502672
    Abstract: A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: November 15, 2022
    Assignee: Eagle Harbor Technologies, Inc.
    Inventors: James R. Prager, Timothy M. Ziemba, Kenneth E. Miller, John G. Carscadden, Ilia Slobodov
  • Patent number: 11502684
    Abstract: A driver circuit includes a high side transistor, a low side transistor, a first trigger circuit, and a second trigger circuit. The high side transistor has a first control terminal and a first current path coupled between a first voltage terminal and an output voltage terminal. The low side transistor has a second control terminal and a second current path coupled between the output voltage terminal and ground. The first trigger circuit is coupled to the first control terminal, the first voltage terminal, and the output voltage terminal. The first trigger circuit is operable to protect the high side transistor. The second trigger circuit is coupled to the second control terminal, the first trigger circuit, and ground. The second trigger circuit is operable to protect the low side transistor.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: November 15, 2022
    Inventors: Sachin Sethumadhavan, Ganapathi Shankar Krishnamurthy
  • Patent number: 11496132
    Abstract: A drive circuit has a control signal input for receiving a first control signal at a first circuit input, an optocoupler which is connected to the control signal input and which is adapted to generate a galvanically decoupled second control signal in accordance with the first control signal, an output circuit for controlling at least one circuit output terminal of the drive circuit in accordance with a third control signal, and an electronic control circuit comprising an energy supply, an input for receiving the second control signal, and an output for outputting the third control signal in accordance with the second control signal received at the input.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 8, 2022
    Assignee: VISHAY SEMICONDUCTOR GMBH
    Inventor: Achim Kruck
  • Patent number: 11489533
    Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 1, 2022
    Assignee: Apple Inc.
    Inventors: Bogdan-Eugen Matei, Hartmut Sturm
  • Patent number: 11476704
    Abstract: A power supply control system controls a redundant power supply system that includes a first power supply system and a second power supply system connected in parallel to a power supply unit. The first power supply system includes a first power supply and a first system. The second power supply system includes a second power supply and a second system. The power supply control system includes a first switch that is a MOSFET provided between the power supply unit and the first power supply, a second switch that is a MOSFET provided between the power supply unit and the second power supply, a wiring configured to supply a dark current flowing from the first power supply to the second system, a first relay of a normally-on type provided on the wiring, and a second relay of a normally-off type provided between the second power supply and the second switch.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 18, 2022
    Assignee: YAZAKI CORPORATION
    Inventor: Atsushi Takahashi
  • Patent number: 11470885
    Abstract: Provided are a power supply drive module, a power supply device and an electronic cigarette, falling within the technical field of electronics. Wherein a first end of the logic controller is connected to a pulse width modulation pin, a second end is connected to a control electrode of the first transistor, and a third end is connected to a control electrode of the second transistor; a first electrode of the first transistor is connected to a voltage input pin, and a second electrode is connected to a switch pin; and a first electrode of the second transistor is connected to the switch pin, and a second electrode is connected to a ground pin. The power supply drive module includes various components integrated on the substrate, so that the volume of the entire power supply drive module is smaller.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 18, 2022
    Assignee: CHANGZHOU PATENT ELECTRONIC TECHNOLOGY CO., LTD.
    Inventor: Weihua Qiu
  • Patent number: 11462616
    Abstract: In the described examples, a driver includes a signal controller that provides a gate control signal to a gate buffer coupled to a gate of a transistor and a field plate control signal to a field plate buffer coupled to a field plate of the transistor. The signal controller provides a rising edge on the field plate control signal causing the field plate buffer to provide a bias voltage on the field plate of the transistor a predetermined amount of time after providing a rising edge on the gate control signal that causes the gate buffer to provide a turn-on voltage on the gate of the transistor that causes the transistor to transition from a cutoff region to a saturation region and to a linear region.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Maurice Khayat, Marco Corsi, Lemuel Herbert Thompson
  • Patent number: 11458930
    Abstract: Start-up of an engine is prevented, and easier installation to a vehicle can be achieved. A device includes: connectors configured to be connected to battery cables of a vehicle; a communication unit configured to communicate with an external device; a power consuming device configured to consume power of a vehicle battery; and an overall control unit configured to perform control of causing consumption of power of the vehicle battery by using the power consuming device, when the overall control unit receives a signal for instructing consumption of the vehicle battery from the external device through the communication unit.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 4, 2022
    Assignee: CLARION CO., LTD.
    Inventor: Haruhiko Sawajiri
  • Patent number: 11463079
    Abstract: The present disclosure provides a power transistor driving method. When a power transistor is turned off, a drain-source voltage of the power transistor is detected, and when the power transistor is an N-type component, and a change rate of the drain-source voltage of the power transistor along with time is lower than a first slope threshold, the power transistor is pulled down in a first current; when the change rate of the drain-source voltage of the power transistor along with the time is higher than the first slope threshold, a driving pole of the power transistor is pulled down in a second current; and when the change rate of the drain-source voltage of the power transistor along with the time is lower than the first slope threshold again, a pull-down switch is turned on or the driving pole of the power transistor is pulled down in a third current.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: October 4, 2022
    Assignee: Joulwatt Technology (Hangzhou) Co., LTD.
    Inventors: Pitleong Wong, Liyu Lin, Xunwei Zhou
  • Patent number: 11463081
    Abstract: A driving circuit includes first and second driving units connected in parallel to each other, wherein both the first and second driving units start to supply a gate current to a gate of a switching device in a turn-on operation of the switching device, when a gate voltage of the switching device increases and has reached a threshold voltage of the switching device, the first driving unit continues to supply the gate current, and the second driving unit stops supply of the gate current before the gate voltage has reached the threshold voltage.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: October 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroshi Yoshida
  • Patent number: 11463085
    Abstract: A semiconductor integrated circuit includes multiple termination circuits that correspond to multiple target pins. The multiple termination circuits each include a first resistor and a first transistor coupled in series between the corresponding target pin and the ground. A second resistor is provided between the corresponding target pin and the control electrode of the first transistor. The enable circuit is arranged such that its output node is coupled to the control electrode of the first transistor, and configured such that (i) when the enable pin is set to the first state, the current is sunk from the output node, and (ii) when the enable pin is set to the second state, the output node is set to the low level.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: October 4, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Koichi Miyanaga