Patents Examined by Metasebia T Retebo
  • Patent number: 10998901
    Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 4, 2021
    Assignee: pSemi Corporation
    Inventors: Ethan Prevost, Michael Conry
  • Patent number: 10992225
    Abstract: The present technology relates to a charge pump circuit that enables reduction of a circuit area. Provided is a charge pump circuit including: a first transistor; a second transistor to which a constant current is supplied; a third transistor connected to the first transistor and a voltage source; a fourth transistor group including N transistors arranged in a cascade on the first transistor side, the N transistors all including control terminals connected to the second transistor; a fifth transistor group including N transistors arranged in a cascade on the second transistor side, the N transistors all including control terminals connected to the second transistor; a first switch that connects the first transistor to the second transistor; a second switch that connects the first transistor to a ground node; a third switch that connects the third transistor to the fifth transistor group; and a fourth switch that connects the third transistor to the ground node.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 27, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Daisuke Arima, Yasuhide Shimizu, Kazuki Goto
  • Patent number: 10985740
    Abstract: A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 20, 2021
    Assignee: Eagle Harbor Technologies, Inc.
    Inventors: James R. Prager, Timothy M. Ziemba, Kenneth E. Miller, John G. Carscadden, Ilia Slobodov
  • Patent number: 10971996
    Abstract: A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 6, 2021
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Eric D. Hunt-Schroeder, John A. Fifield, Dale E. Pontius
  • Patent number: 10972090
    Abstract: An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: April 6, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yu-Wen Chang, Leng-Nien Hsiu, Isaac Y. Chen
  • Patent number: 10965281
    Abstract: An electronic circuit provided with a III/V semiconductor domain, and a method of operating such a circuit is presented. In particular, the present application relates to electronic circuit based on a Gallium Nitride (GaN) semiconductor. GaN components must be controlled in a way that ensures proper operation over a wide variation of GaN parameters. There is a circuit comprising a first domain coupled to a second domain, the first domain being based on a III/V semiconductor; wherein the first domain comprises a first component and a second component. The second component being representative of an electrical characteristic of the first component. The second domain contains a sensor adapted to sense an electrical quantity of the second component and an input generator coupled to the sensor. The input generator is adapted to provide at least one input, based on the electrical quantity, to the first domain.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 30, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Christoph Nagl, Nebojsa Jelaca, Horst Knoedgen
  • Patent number: 10965156
    Abstract: A controlled wireless Capacitive Power Transfer (CPT) system includes a primary side for wirelessly transmitting power to a secondary side via coupling plates having mutual capacitance CM. A primary adaptive matching network regulates the current flowing to the secondary side. A primary controller includes a first control loop for adjusting the switching frequency fsw to compensate for changes in the impedance of the primary matching network. A second control loop adjusts the resonant frequency of the primary resonant circuit to track the switching frequency fsw. A secondary adaptive matching network is comprised of a secondary resonant circuit with a bias-controlled variable secondary inductor serially connected to the mutual capacitance CM and a capacitor parallelly connected to the mutual capacitance CM, for matching the impedance of the secondary matching network. A secondary controller adjusts the impedance of the secondary matching network to match the resonant frequency of the primary resonant circuit.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 30, 2021
    Assignee: B. G. Negev Technologies and Applications Ltd., At Ben-Gurion University
    Inventor: Mor Mordechai Peretz
  • Patent number: 10958268
    Abstract: Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be careless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith Kin Leong, Thomas Ferianz
  • Patent number: 10951025
    Abstract: A hybrid energy storage system includes at least one first energy store and at least a second energy store, each with a nominal energy flow at least in one direction, wherein the energy stores exchange electrical energy with one another and/or with at least one external energy source and/or energy sink via electro-physical energy flows, using at least one control circuit. The control circuit operates the energy sink using at least one boost converter, which has at least one electronic switch, and/or a buck converter in the event of a required energy flow of the energy sink which is higher than the nominal energy flow of the second energy store, with an energy flow of the first energy store, while the second energy store supplies an energy flow from zero up to a constant energy flow which corresponds at maximum to the nominal energy flow of the second energy store.
    Type: Grant
    Filed: November 18, 2017
    Date of Patent: March 16, 2021
    Assignee: RUTRONIK ELEKTRONISCHE BAUELEMENTE GMBH
    Inventors: Ringo Lehmann, Lutz Zacharias, Mirko Bodach, Sven Slawinski, Andreas Mangler, Markus Krieg
  • Patent number: 10940768
    Abstract: A main relay protection device includes a motor generator, a rechargeable driving battery, an externally-coupled charger, a main relay, a charging bus bar, a charging relay, a main relay temperature sensor, and a controller. The motor generator drives a vehicle. The battery supplies power to the motor generator. The charger charges the battery. The main bus bar is disposed between the battery and the motor generator. The main relay is disposed in the main bus bar. The charging bus bar is disposed between the main bus bar and the charger. The charging relay is disposed in the charging bus bar. The sensor is configured to detect a temperature of the main relay. The controller performs ON-control on the charging relay in a state where the main relay is turned on, if the detected temperature of the main relay is higher than or equal to a preset heat radiation starting threshold.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 9, 2021
    Assignee: SUBARU CORPORATION
    Inventors: Hiroto Asai, Yo Masuda, Takanobu Nishikori, Kohei Takei
  • Patent number: 10936000
    Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Ryan Hanschke, Filippo Marino, Sunglyong Kim, Tobin Daniel Hagan, Richard Lee Valley, Bharath Balaji Kannan, Salvatore Giombanco, Seetharaman Sridhar
  • Patent number: 10938388
    Abstract: According to one embodiment, a control circuit is connected to an element portion including a first element. The first element includes a first gate, a first collector, and a first emitter. The control circuit performs a first operation and a second operation. In at least a portion of the first operation, the control circuit causes a first current to flow from the first collector toward the first emitter. In at least a portion of the second operation, the control circuit causes a second current to flow from the first emitter toward the first collector. A first time constant of a switching of the first element in the first operation is different from a second time constant of a switching of the first element in the second operation.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsunori Sakano, Kazuto Takao
  • Patent number: 10931236
    Abstract: Provided is a detector circuit that includes: a first transistor that has an alternating current signal input to a base thereof, and that outputs a first detection signal that depends on the alternating current signal from a collector thereof; a second transistor that has the first detection signal input to a base thereof, and that outputs a second detection signal that depends on the first detection signal from a collector thereof; and an alternating current signal path along which the alternating current signal is supplied to the base of the second transistor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 23, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasutaka Sugimoto, Hiroyuki Hirooka
  • Patent number: 10931287
    Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yasuhiro Takai, Martin Brox, Mani Balakrishnan, Maksim Kuzmenka
  • Patent number: 10931295
    Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 23, 2021
    Assignee: eTopus Technology Inc.
    Inventor: Danfeng Xu
  • Patent number: 10924123
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Patent number: 10908558
    Abstract: A circuit device includes a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first and second clock signals, and a PLL circuit adapted to perform phase synchronization between the first and second clock signals.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 2, 2021
    Inventors: Takashi Kurashina, Katsuhiko Maki
  • Patent number: 10897252
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an auxiliary channel. The auxiliary channel may include a first PMOS transistor connected between two terminals of the auxiliary channel and a second PMOS transistor connected to one of the two terminals, via a resistor, at a first end and to a gate terminal of the first PMOS. The auxiliary channel may further include a support circuit connected to the gate terminals of both the first and second PMOS transistors.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: January 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Athar Ali Khan. P, Rajiv Pandey, Yogendri Ramsingh
  • Patent number: 10897245
    Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abishek Manian
  • Patent number: 10892744
    Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael Koch, Matthias Ringe, Andreas Arp, Fatih Cilek