Abstract: An electronic circuit that recognizes a disconnected state from an outside during disconnection of a power supply line is provided. For this purpose, an electronic circuit includes: a load provided between a power supply line and an output terminal in the electronic circuit; a transistor provided between the load and the output terminal; a current generation circuit that generates current using a power supply voltage at a power supply line in the electronic circuit; and a control circuit that controls the transistor using a control voltage that changes according to the current generated by the current generation circuit.

Abstract: A bootstrapped switch circuit coupled to a timing circuit. The bootstrapped switch circuit comprises a charge pump coupled to the timing circuit. The bootstrapped switch circuit also comprises a logic circuit coupled to the output of the charge pump and the timing circuit. The logic circuit is capable of generating multiple control signals which can independently control the turn-on of switches in the voltage path between the inputs and outputs of the bootstrapped switch circuit.

Abstract: Provided is a switch having a structure having an excellent isolation characteristic even without a limiter in an ultrahigh frequency hand used for a military component. A switch according to an embodiment of the present invention comprises: multiple transistors which are connected in parallel to a path from an input terminal toward an output terminal and perform switching; and a first transmission line provided between the input terminal and a node on a path to which a first transistor is connected. By the present invention, switching can be performed in an ultrahigh frequency such as W-band while a GaN transistor is used, an insertion loss is low, an isolation characteristic is excellent, and eventually efficiency of an ultrahigh frequency circuit can be further enhanced.

Abstract: A hybrid switch for a power converter and a method of operating said hybrid switch, the hybrid switch comprising: at a minimum a first and a second element comprising one or more switching devices of a first semiconductor type, and at a minimum a third element comprising one or more switching devices of a second semiconductor type, wherein the second semiconductor type is different from the first semiconductor type, and wherein each element is independently configurable and connected to a separate respective control terminal; and, a controller connected to the control terminals, wherein the controller is configured to control each element independently through each respective control terminal, and wherein the controller is further configured to activate elements based on a measured or estimated current and/or power as required by an operating condition of the converter.

Abstract: A common gate input circuit for III/V D-mode Buffered FET Logic (BFL) maximizes the dynamic range to drive a level shift section to set the proper voltage levels to switch the BFL and allows for decoupling of the switch point from the dynamic range. A common gate switching section includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate connected in series between high and low supplies Vdd and Vee1 (typically ground potential). The gate electrode of FET2 is coupled to Vee1 and the source electrode of FET2 is driven by the external digital signals. This eliminates the additional supply Vss, thus maximizing the dynamic range of the section to switch between Vdd and Vee1 and decouples the dynamic range from the switch point. An input level shift section may shift the Data In to the source electrode of FET2 to shift the switch point and to present a high input impedance.

Abstract: Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Abstract: Drive circuits and methods control a switching output stage. The drive circuit includes a control drive circuit coupled to a control node of a low side power transistor and a switching node of a switching output stage. The control drive circuit includes a slew rate control circuit to control the adjusted drive current on the control node of the low side power transistor responsive to the slew rate of the output voltage to cause the low side power transistor to provide a constant slew rate for the output voltage over a range of values for the output current. A reverse detector circuit is coupled to the switching node and to a control node of a high side power transistor in the switching output stage. The reverse detector circuit controls activation of the high side power transistor in response to the output voltage on the switching node reaching a switching threshold.

Abstract: A semiconductor device includes a semiconductor chip, and an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip such as to be individually controlled and that is configured such as to generate a single output signal by selective controls of the n-number of system transistors.

Abstract: A switch device includes: a voltage dividing circuit that outputs a voltage dividing value corresponding to a conduction state of each of a first switch and a second switch to an output line; an operation interface including a dial which rotates in accordance with a user operation; a rotation detection circuit that detects (i) rotation of the dial by a predetermined angle and (ii) a rotation direction of the dial, and generates an angle signal which includes a pulse indicating detection of the rotation by the predetermined angle, and a direction signal which indicates whether the rotation direction is a first direction or a second direction; and a selection circuit that selects whether to output the pulse of the angle signal to control the first switch or to output the pulse to control the second switch, according to whether the direction signal indicates the first or the second direction.

Abstract: A high power factor control circuit is disclosed, which is used in an AC/DC converter. The converter includes a rectification module, a conversion module and a load. The rectification module receives AC power and rectifies it into a DC current, and the conversion module converts the DC current to drive power as desired by the load and provides it to the load. The conversion module includes a conversion element including an inductive element and a switching element. The control circuit includes a peak limiting signal generator and a switching element control module. The peak limiting signal generator receives a reference signal and produces at least one peak limiting signal from a sample signal. The switching element control module is configured to control switching of the switching element so that, within at least half a line-frequency period, a value of the ripple in the output current flowing through the load is not greater than a limit value.

Abstract: A gate driver includes a gate current circuit and a driver logic circuit. The gate current circuit has a gate current circuit output and includes first and second current sources coupled to the gate current circuit output. The driver logic circuit has a capacitor and is configured to: charge and discharge the capacitor to generate a detect voltage across the capacitor; cause the first current from the first current source to flow to the gate current circuit output in response to a voltage on the gate current circuit output being below the detect voltage; and cause the second current from the second current source to flow to the gate current circuit output in response to the voltage on the gate current circuit output being above the detect voltage.

Abstract: A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

Abstract: A circuit comprises a first pulse-width modulator configured to generate a first pulse based on a first input, a second pulse-width modulator configured to generate a second pulse based on a second input, a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, and a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor. A gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input.

Abstract: A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers. A switching driver has first and second supply node for receiving supply voltages and includes an output bridge stage, a capacitor and a network of switches. The network of switches is operable in different switch states to provide different switching voltages to the output bridge stage. A controller is configured to control the switch state of the network of switches and a duty cycle of output switches of the output bridge stage based on an input signal to generate an output signal for driving the transducer.

Abstract: A drive circuit is provided. When the switching element is in turn-on state and a collector-emitter voltage of the switching element is equal to or higher than a first predetermined voltage value, the first diode is turned on; the first transistor and the second transistor are turned on; and, after a mask time in which a first capacitor is started to be charged with a current from a current source and a voltage value at two ends becomes equal to or higher than a second predetermined voltage value higher than the first predetermined voltage value, an abnormality detection signal is output to the control unit. The control unit stops an output of the pulse signal to the switching element in response to the abnormality detection signal.

Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.

Abstract: The present invention provides a driving circuit for a driving hip. The driving circuit includes a bootstrap circuit with a bootstrap voltage terminal. A power terminal of a high-voltage driving circuit is connected to the bootstrap voltage terminal, and a ground terminal of the high-voltage driving circuit is connected to a regulating terminal. A high-side drive circuit includes a high-side pull-up circuit and a high-side pull-down circuit. The driving circuit includes: an auxiliary power terminal; a mirror current source an input terminal of the mirror current source being connected to the bootstrap voltage terminal; a first MOS transistor; a second MOS transistor an equivalent diode component, an output terminal of the second MOS transistor being connected to the regulating terminal through the equivalent diode component; and an equivalent resistance component, the gate of the first MOS transistor being connected to the regulating terminal through the equivalent resistance component.

Abstract: A gate driving device includes an operational amplifier, two impedances, a multiplexer, and an UVLO circuit. The operational amplifier has an output coupled to the gate of the SiC MOSFET, a positive power terminal coupled to a positive power rail, and a negative power terminal coupled to a negative power rail. The impedances are coupled in series and coupled between the output of the amplifier and a low-voltage terminal. The UVLO circuit is coupled to the multiplexer and the positive power rail and coupled to the positive power voltage of the positive power rail, a driving voltage, and an UVLO voltage. The UVLO circuit controls the multiplexer to transmit an off voltage or an on voltage to the positive input of the operational amplifier based on the positive power voltage, the driving voltage, and the UVLO voltage, thereby turning on or off the SiC MOSFET.

Abstract: A semiconductor device includes a magnetic switch provided on a semiconductor substrate. The magnetic switch includes: a Hall element, first and second power supply terminals; a current source driving the Hall element; a switch circuit switching a differential output voltage supplied from two electrodes of the Hall element to a first or second state based on a control signal supplied from a control terminal; an amplifier amplifying a signal from the switch circuit; a reference voltage circuit generating a reference voltage based on a reference common mode voltage and a control signal; a comparator receiving an output signal of the amplifier and the reference voltage; and a latch circuit latching an output voltage of the comparator. The reference voltage of the reference voltage circuit is controlled by switching from a reference value to a voltage with a high or low adjustment value according to the output voltage of the comparator.