Patents Examined by Metasebia T Retebo
  • Patent number: 11876437
    Abstract: According to some embodiments, a half-bridge circuit is provided. The half-bridge circuit includes a substrate, a monolithic die over the substrate, a switch node, a high-side switch integrated with the monolithic die and coupled to the switch node, and a conductive structure including a first terminal coupled to the substrate and a second terminal coupled to the switch node.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 16, 2024
    Assignee: Infineon Technologies Austria AG
    Inventor: Kennith Kin Leong
  • Patent number: 11870429
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: January 9, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Patent number: 11870430
    Abstract: An over-current protection circuit for composite transistor devices is provided, connected between an input terminal and a load, and including: a control-terminal voltage-generation module whose output voltage varies with its input voltage when driven by a first voltage, wherein the output voltage of the control-terminal voltage-generation module serves as a control-terminal voltage; a composite transistor device, connected between the control-terminal voltage-generation module and the load, configured to conduct in response to the control-terminal voltage and a second voltage to generate an output current flowing through the load; and an over-current protection module, connected between the composite transistor device and the load, wherein when the output current of the composite transistor device exceeds a preset limit, a clamping voltage is applied to the composite transistor device by the over-current protection module to limit a current flowing through the composite transistor device, thereby limiting th
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: January 9, 2024
    Assignee: MICROTERA SEMICONDUCTOR (GUANGZHOU) CO., LTD.
    Inventors: Franco Maloberti, Alper Akdikmen, Yao Liu, Sen Liu, Jianping Li, Xinglong Liu, Linsen Shi, Guichun Ban, Xiaowei Liu, Haibin Liu, Huahua Duan, Chao Yang, Jie Yin
  • Patent number: 11863163
    Abstract: A digital high-speed hybrid load pull test system comprises a slide screw automatic passive tuner, a digital active forward injection loop in a closed loop transmission configuration, calibration and tuning algorithms. The forward active injection loop comprises at least one adjustable coupler, a digital electronic tuner and feedback power amplifier; the passive tuner comprises one or more metallic tuning probes, used to create passive reflection factors. Small signal calibration of the passive and active tuners create a global calibration data base, used to pre-tune in the area of the target impedance and final high power (nonlinear) tuning employs a in-situ signal power wave search and measurement for digital impedances around the small signal pattern. The system provides for high speed low injected power tuning with maximum reflection factor at DUT reference plane reaching unity.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: January 2, 2024
    Inventor: Christos Tsironis
  • Patent number: 11855620
    Abstract: A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chin Hua Wen
  • Patent number: 11848325
    Abstract: A load drive device includes a semiconductor element and a current detection resistor. The semiconductor element includes a first main electrode provided on a front surface side and having a higher potential and a second main electrode provided on a back surface side opposite to the front surface and having a lower potential than the first main electrode. The second main electrode is divided such that the semiconductor element includes a main element that supplies electric power to a load in response to the main element being turned on and a sense element that detects a current. The current detection resistor is connected in series to the sense element and provided between the second main electrode of the sense element and the second main electrode of the main element.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: December 19, 2023
    Assignee: DENSO CORPORATION
    Inventor: Jun Fukuhara
  • Patent number: 11838016
    Abstract: A circuit, intended to be associated in series with a load to be powered including a first field-effect transistor; at least one second field-effect transistor, associated in parallel with the first transistor; and at least one sensor of information representative of a current transmitted to said load, the gate of the second transistor being coupled to an output of the sensor.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: December 5, 2023
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: René Escoffier, Julien Buckley
  • Patent number: 11838017
    Abstract: Apparatus for performing substrate voltage management is provided herein and comprises an active substrate voltage management circuit configured to be coupled to a substrate of a bidirectional gallium nitride high electron mobility transistor comprising a first source and a second source. The active substrate voltage management circuit comprises a first circuit that is connected to the first source and a second circuit that is connected to a second source such that when the bidirectional gallium nitride high electron mobility transistor is operational one of the first circuit or the second circuit connects one of the first source to the substrate or the second source to the substrate, respectively, to control a bias voltage applied to the substrate.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: December 5, 2023
    Assignee: Enphase Energy, Inc.
    Inventors: Michael J. Harrison, Christiaan Johannes van Antwerpen, Patrick Lyle Chapman
  • Patent number: 11824548
    Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 21, 2023
    Assignee: XILINX, INC.
    Inventors: Shaojun Ma, Chi Fung Poon
  • Patent number: 11824527
    Abstract: An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 21, 2023
    Assignee: AMS AG
    Inventors: Jeffrey Smith, Pawel Chojecki
  • Patent number: 11817852
    Abstract: The present disclosure discloses an anti-backflow output switch, a collector of the tertiary tube Q6 is connected to the source of the MOS tube Q4 through a resistor R24 and a diode ZD2, a resistor R30 is connected between the source and the gate of the MOS tube Q4, the drain of the MOS tube Q4 is connected to the drain of the MOS tube Q9, a resistor R25 and a diode D5 are connected to the gate of the MOS tube Q9, a resistor R28 is connected between the gate and the source of the MOS tube Q9, a resistor R33 is connected between the drain of the MOS tube Q10, a resistor R37 is connected between the gate and the source of the MOS tube Q10, the gate of the MOS tube Q10 is connected to a first pin of the chip U2 through a resistor R35, a resistor R34 and a resistor R38 are connected to the second pin and the third pin of the chip U2 respectively, a resistor R39 and a capacitor C35 are connected between the first pin and the second pin of the chip U2, the second pin of the chip U2 is connected to a fourth pin of t
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: November 14, 2023
    Assignees: MASS POWER ELECTRONICS INC., GUANGZHOU BOJU INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Wanxiong Chen, Zanxing Luo, Xiaosheng Zheng, Zhuo Jia
  • Patent number: 11811389
    Abstract: A real-time clock device includes a package that houses a resonator, an oscillation circuit, a clocking circuit, and a functional circuit, and on which external terminals are formed.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: November 7, 2023
    Inventor: Toshiya Usuda
  • Patent number: 11804834
    Abstract: An electromagnetic interference regulator by use of capacitive parameters of the field-effect transistor for detecting the induced voltage and the induced current of the field-effect transistor to determine whether the operating frequency of the field-effect transistor is within the preset special management frequency of electromagnetic interference. When the basic frequency and the multiplied frequency exceed the limit, the content of the external capacitor unit can be adjusted to assist the products using field-effect transistors to maintain excellent electromagnetic interference adjustment capabilities under various loads, thereby optimizing the characteristics of electromagnetic interference.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: October 31, 2023
    Assignee: POTENS SEMICONDUCTOR CORP.
    Inventors: Wen Nan Huang, Ching Kuo Chen, Shiu Hui Lee, Hsiang Chi Meng, Cho Lan Peng, Chuo Chien Tsao
  • Patent number: 11791816
    Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers. A switching driver has first and second supply node for receiving supply voltages and includes an output bridge stage, a capacitor and a network of switches. The network of switches is operable in different switch states to provide different switching voltages to the output bridge stage. A controller is configured to control the switch state of the network of switches and a duty cycle of output switches of the output bridge stage based on an input signal to generate an output signal for driving the transducer.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: October 17, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Axel Thomsen, Eric J. King, Anthony S. Doy, Thomas H. Hoff, John L. Melanson
  • Patent number: 11777493
    Abstract: A driving circuit includes: a primary driver configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driver connected to an output terminal of the primary driver and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: October 3, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan Gu
  • Patent number: 11777495
    Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers where the switching driver has an output bridge stage for switching an output node between switching voltages and a modulator for controlling the duty cycle of the output bridge stage based on an input signal. The switching driver also includes a voltage controller for providing the switching voltages which is operable to provide different switching voltages in different driver modes. A controller is provided to control the driver mode of operation and the duty cycle of the switching driver based on the input signal, and the controller is configured to transition from a present driver mode to a new driver mode by controlling the voltage controller to provide the switching voltages for the new mode and controlling the modulator to vary the duty cycle of the output bridge stage. The change in duty cycle is controlled such that there is no substantial discontinuity in switching ripple due to the mode transition.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: October 3, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: John L. Melanson, Eric J. King, Thomas H. Hoff, Axel Thomsen
  • Patent number: 11777494
    Abstract: A level shift transistor of a first conductivity type configured to level shift a signal from a primary side circuit to a secondary side circuit between the primary side circuit having a primary side reference potential as reference and the secondary side circuit having a secondary side reference potential independent from the primary side reference potential as reference, a diode connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit, a capacitor connected in parallel to the diode, and an inverter configured to invert the signal are provided. A control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit, and a second main electrode thereof is connected to an output of the inverter. The inverter operates between the primary side reference potential and the primary side power supply.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 3, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuta Tsukuma, Hiroshi Yoshida
  • Patent number: 11777499
    Abstract: A switching circuit comprises a first series switch coupled to a first output port, the first series switch including a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, a second series switch coupled to a second output port, and coupling circuitry configured to couple a gate of the fifth FET and a gate of the sixth FET to a first node, a source of the fifth FET and a drain of the sixth FET to a second node, a source of the first FET and a drain of the second FET to a third node, a gate of the first FET and a drain of the fifth FET to a fourth node, a gate of the second FET and a source of the sixth FET to a fifth node, the fourth node and the fifth node to a first gate voltage, and the first node to a second gate voltage that is different than the first gate voltage.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: October 3, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Lui Ray Lam
  • Patent number: 11777507
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Patent number: 11764758
    Abstract: A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 19, 2023
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Takahashi