Patents Examined by Metasebia T Retebo
  • Patent number: 11683032
    Abstract: A power semiconductor device of the present disclosure includes: a first switching element; a second switching element connected in parallel to the first switching element, and having a higher short circuit capability than the first switching element; drive circuits to drive the first switching element and the second switching element; and determination circuits to compare a target current as a sum of a current flowing through the first switching element and a current flowing through the second switching element to a first threshold and a second threshold greater than the first threshold. The drive circuits switch off the first switching element when the determination circuits determine that the target current is equal to or greater than the first threshold, and switch off the second switching element when the determination circuits determine that the target current is equal to or greater than the second threshold.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: June 20, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hisashi Oda
  • Patent number: 11680978
    Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Ann Lai, Ruo-Rung Huang, Kun-Lung Chen, Chun-Yi Yang, Chan-Hong Chern
  • Patent number: 11677396
    Abstract: Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: June 13, 2023
    Assignee: GaN Systems Inc.
    Inventors: Juncheng Lu, Larry Spaziani
  • Patent number: 11675046
    Abstract: Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: June 13, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: See Taur Lee, Sher Jiung Fang
  • Patent number: 11664570
    Abstract: A method of multiplexing control lines of a qubit array includes applying a qubit control signal to a single driveline. The qubit control signal is split on the single driveline between a first resonator and a second resonator. The first driveline is operative to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit by the first resonator. The third qubit is coupled to the fourth tunable qubit by the second resonator. A variation in amplitude of the qubit control signal is compensated by adjusting a frequency of the second tunable qubit and a frequency of the fourth tunable qubit.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: May 30, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Devin Underwood, Jiri Stehlik, David Zajac
  • Patent number: 11664718
    Abstract: A transistor device includes a transistor and programmable controller. The controller has an output that controls operation of the transistor. The controller includes analog computing circuitry and optionally digital computing circuitry that may be used to setup the analog computing circuitry. In addition to two connectors for connecting the transistor into an external circuit, the device includes a further connector that provides an input to the controller and through which the control can be programmed post manufacture. The transistor device may be a discrete component in which transistor and controlling circuitry are held in packaging, the three connectors exposed through the packaging in order to connect the device to an external circuit.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 30, 2023
    Assignee: Know Moore, Ltd.
    Inventor: David Summerland
  • Patent number: 11664795
    Abstract: A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: May 30, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi Kurachi
  • Patent number: 11658657
    Abstract: An integrated circuit includes a first stacked transistor switch having a current path coupled between a first tuning element port and a second tuning element port; a second stacked transistor switch having a current path coupled between the first tuning element port and a ground port; and a control circuit coupled to a control node of the first stacked transistor switch and coupled to a control node of the second stacked transistor switch, wherein a series on-resistance of the first stacked transistor switch is greater than a series on-resistance of the second stacked transistor.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: May 23, 2023
    Assignee: Infineon Technologies AG
    Inventor: Kun Wang
  • Patent number: 11658658
    Abstract: In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: May 23, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijit Kumar Das, Brian Roger Elies
  • Patent number: 11658656
    Abstract: A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunchul Hwang, Youngo Lee
  • Patent number: 11652409
    Abstract: Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo
  • Patent number: 11636315
    Abstract: According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 25, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Kumiko Nomura, Yoshifumi Nishi
  • Patent number: 11632104
    Abstract: According to one embodiment, a semiconductor device includes a first switch element including a first end to which a first voltage is applied, and a second end and a gate electrically coupled to a first node, a second switch element including a first end to which a second voltage is applied, and a second end and a gate electrically coupled to the first node, a third switch element including a first end to which the second voltage is applied, a second end electrically coupled to a second node, and a gate coupled to the first node, a fourth switch element including a gate coupled to the second node, and a first terminal electrically coupled to a first end of the fourth switch element and outputting a signal based on a voltage of the second node.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: April 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tsuneyuki Hayashi
  • Patent number: 11632041
    Abstract: The present disclosure provides power semiconductor module, comprising at least three non-jumping power terminals at a non-jumping potential, wherein multiple power semiconductors and at least one first capacitor are integrated within a package and electrically connected between a first non-jumping power terminal and a second non-jumping power terminal of the at least three non-jumping power terminals; and at least one jumping power terminal at a jumping potential. A first jumping power terminal of the at least one jumping power terminal is electrically connected to one terminal of a power inductor and a third non-jumping power terminal of the at least three non-jumping power terminals is electrically connected to the other terminal of the power inductor; wherein at least one second capacitor is electrically connected between the third non-jumping power terminal and at least one of other non-jumping power terminals.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: April 18, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chao Yan, Liping Sun
  • Patent number: 11619955
    Abstract: A switch circuit configured to receive power from either a single power source or dual power source. The circuit includes two power input terminals and two power output terminals. For a single power source, the switch circuit may receive the single power source at either of the two power input terminals. The switch circuit provides power to a load without regard to which of the power input terminals the single power source is connected. The switch circuit shorts the power output terminals for a single power input, which provides power at both power output terminals. For a dual power source system, the switch circuit may isolate the two power output terminals so each power output terminal may operate independently without shorting. In some examples, the switch circuit may be part of a thermostat or similar HVAC system controller.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 4, 2023
    Assignee: Ademco Inc.
    Inventors: Hyunki Kim, Robert D. Juntunen
  • Patent number: 11616494
    Abstract: First and second switches are connected in series between first and second terminals. A third switch is provided between a first node between the first terminal and the first switch, and a first resistive-element. A fourth switch is provided between a second node between the first and second switches, and the reference power-source. A controller switches the first to fourth switches between conduction and non-conduction states. First, third, fifth, and seventh delay-circuits are provided between the first to fourth switches and the controller and delay first, second, third, fourth control signals for switching the first to fourth switches from a conduction state to a non-conduction state, respectively. Second, fourth, sixth, and eighth delay-circuits are provided between the first to fourth switches and the controller and delay the first, second, third, fourth control signals for switching the first to fourth switches to a non-conduction state to a conduction state, respectively.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: March 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Satoshi Katou, Hideo Arimoto
  • Patent number: 11606027
    Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: March 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chia Liang Tai
  • Patent number: 11606089
    Abstract: A decoupling capacitance (decap) system which includes: a decap circuit electrically coupled between a first or second reference voltage rail and a first node; and a biasing circuit coupled between the first node and correspondingly the second or first reference voltage rail. Due to the series connection between the decap circuit and the biasing circuit, the voltage drop across the biasing circuit effectively reduces the voltage drop across the decap circuit so that the voltage drop across the decap circuit is less than a voltage drop across the decap system as whole.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Lin Liu, Yi-Hsiang Wang, Jaw-Juinn Horng
  • Patent number: 11595038
    Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 28, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Yasuhiro Yamada, Hidekazu Umeda
  • Patent number: 11588356
    Abstract: A wireless power transmission system comprising a wireless power transmitting device and a wireless power receiving device. The wireless power receiving device is configured to regulate power drawn during a power transfer phase to maintain a substantially steady power level that is less than or equal to a power consumption level demanded by an associated load. The wireless power transmitting device is configured to determine the presence of a foreign object by monitoring the power transmitted or the power received and identifying a characteristic change in steady state power indicative of the presence of a foreign object.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 21, 2023
    Assignee: Apple Inc.
    Inventor: Jeffrey Douglas Louis