Patents Examined by Metasebia T Retebo
  • Patent number: 11777499
    Abstract: A switching circuit comprises a first series switch coupled to a first output port, the first series switch including a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, a second series switch coupled to a second output port, and coupling circuitry configured to couple a gate of the fifth FET and a gate of the sixth FET to a first node, a source of the fifth FET and a drain of the sixth FET to a second node, a source of the first FET and a drain of the second FET to a third node, a gate of the first FET and a drain of the fifth FET to a fourth node, a gate of the second FET and a source of the sixth FET to a fifth node, the fourth node and the fifth node to a first gate voltage, and the first node to a second gate voltage that is different than the first gate voltage.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: October 3, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Lui Ray Lam
  • Patent number: 11777507
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Patent number: 11764186
    Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 19, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Bharani Chava, Abinash Roy
  • Patent number: 11764758
    Abstract: A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 19, 2023
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Takahashi
  • Patent number: 11757443
    Abstract: An electrical switching system includes a constant-power controller and a switching device electrically coupled between a first node and a second node. The constant-power controller is configured to (a) generate a digital control signal to control the switching device, (b) control a duration of an active phase of the digital control signal at least partially based on a voltage across the switching device, and (c) control a peak value of the digital control signal to regulate a peak magnitude of current flowing through the switching device.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: September 12, 2023
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Pietro Filoramo, Benedetto Marco Marletta, Carmelo Francesco Maria Marchese, Angelo Genova
  • Patent number: 11757290
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: September 12, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11742847
    Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: August 29, 2023
    Assignee: pSemi Corporation
    Inventors: Ethan Prevost, Michael Conry
  • Patent number: 11742848
    Abstract: Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: August 29, 2023
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Gregory Szczeszynski
  • Patent number: 11736103
    Abstract: A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 22, 2023
    Assignee: Appleton Grp LLC
    Inventors: Joel Jeremiah Guevarra Atienza, Mark Chester Bernardino Nepomuceno, Jonathan Art Fulgencio Recaflanca, Runelle Namoro Tria
  • Patent number: 11736105
    Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Abhinav Murali, Pradeep Kumar Sana, Sajin Mohamad, Harikrishna Chintarlapalli Reddy, Rakesh Kumar Sinha, Jibu Varghese K
  • Patent number: 11728788
    Abstract: A digital high-speed hybrid load pull test system comprises a slide screw automatic passive tuner, a digital active forward injection loop in a closed loop transmission configuration, calibration and tuning algorithms. The forward active injection loop comprises at least one adjustable coupler, a digital electronic tuner and feedback power amplifier; the passive tuner comprises one or more metallic tuning probes, used to create passive reflection factors. Small signal calibration of the passive and active tuners create a global calibration data base, used to pre-tune in the area of the target impedance and final high power (nonlinear) tuning employs a in-situ signal power wave search and measurement for digital impedances around the small signal pattern. The system provides for high speed low injected power tuning with maximum reflection factor at DUT reference plane reaching unity.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: August 15, 2023
    Inventor: Christos Tsironis
  • Patent number: 11728793
    Abstract: A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: August 15, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11728794
    Abstract: A data receiving circuit is provided. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latch circuit. The first transistor has a gate configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 15, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11716078
    Abstract: In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: August 1, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajdeep Bondade, Maxim Franke, Stephen Phillip Savage, Mrinal Kanti Das, Johan Tjeerd Strydom
  • Patent number: 11714443
    Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Anupriya Chakraborty, John David Porter, Alan John Wilson
  • Patent number: 11711073
    Abstract: A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: July 25, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Andrew Joseph Thomas
  • Patent number: 11711003
    Abstract: An electric power supply is disclosed having high-voltage, direct-current (HVDC) circuitry comprising one or more DC pre-charge capacitors and one or more power transistor switches, the HVDC circuitry configured to receive high-voltage, direct-current (HVDC) input power of about 320 volts and/or greater and convert the HVDC input power to multi-phase, high-voltage, alternating-current (HVAC) output power of about 320 volts and/or greater; and low-voltage, direct current (LVDC) circuitry adapted and configured to operate on low-voltage, direct-current, wherein the LVDC circuitry is configured to control and monitor the multi-phase HVAC output power. The electric power supply is further configured to operate in reverse and convert received multiphase HVAC input power to HVDC output power.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: July 25, 2023
    Assignee: MAGNIX USA, INC.
    Inventors: Youcef Abdelli, Roei Ganzarski
  • Patent number: 11705803
    Abstract: A gate driver is configured to drive a normally-on device and a normally-off device coupled in series. The gate driver controls the normally-on device in response to a PWM signal, and to control a normally-off device to maintain ON in normal operations. If an under voltage condition of a negative power supply of a first driver used to drive the normally-on device, or a positive power supply of a second driver used to drive the normally-off device, or an input supply voltage is detected, the normally-off device is controlled to be OFF.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: July 18, 2023
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Di Han, Jian Jiang
  • Patent number: 11699721
    Abstract: The present disclosure relates to a novel integrate-and-fire (IF) neuron circuit using a single-gated feedback field-effect transistor (FBFET) to realize small size and low power consumption. According to the present disclosure, the neuron circuit according to one embodiment may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a threshold value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a single-gated feedback field-effect transistor connected to the capacitor. Then, the neuron circuit may reset the generated spike voltage using transistors connected to the feedback field-effect transistor.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 11, 2023
    Assignee: Korea University Research and Business Foundation
    Inventors: Sang Sig Kim, Kyoung Ah Cho, Sol A Woo, Doo Hyeok Lim, Jin Sun Cho, Young Soo Park
  • Patent number: 11689195
    Abstract: In general, according to one embodiment, a semiconductor device includes a first terminal, a second terminal and a first circuit. The first circuit includes a first switching element, a second switching element and a first resistor. The gate of the first switching element is coupled between the first node and the second terminal. The first resistor and the second switching element are coupled in series between the first node and the second terminal. The first circuit is configured to change the first switching element and the second switching element from an off state to an on state when supply of the first voltage to the first node is stopped.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: June 27, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Naoya Yonehara, Shuji Toda, Masatoshi Watanabe, Takaaki Kakumu