Abstract: A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.

Abstract: A gate driver is configured to drive a normally-on device and a normally-off device coupled in series. The gate driver controls the normally-on device in response to a PWM signal, and to control a normally-off device to maintain ON in normal operations. If an under voltage condition of a negative power supply of a first driver used to drive the normally-on device, or a positive power supply of a second driver used to drive the normally-off device, or an input supply voltage is detected, the normally-off device is controlled to be OFF.

Abstract: The present disclosure relates to a novel integrate-and-fire (IF) neuron circuit using a single-gated feedback field-effect transistor (FBFET) to realize small size and low power consumption. According to the present disclosure, the neuron circuit according to one embodiment may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a threshold value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a single-gated feedback field-effect transistor connected to the capacitor. Then, the neuron circuit may reset the generated spike voltage using transistors connected to the feedback field-effect transistor.

Abstract: In general, according to one embodiment, a semiconductor device includes a first terminal, a second terminal and a first circuit. The first circuit includes a first switching element, a second switching element and a first resistor. The gate of the first switching element is coupled between the first node and the second terminal. The first resistor and the second switching element are coupled in series between the first node and the second terminal. The first circuit is configured to change the first switching element and the second switching element from an off state to an on state when supply of the first voltage to the first node is stopped.

Abstract: A power module (10) for operating an electric vehicle drive includes a current input configured for supplying an input current. The current input includes multiple contact elements (182, 184). Multiple circuit-breakers (142, 144) are configured for generating an output current based on the supplied input current. A current output (192) is configured for outputting the output current at a consumer. A substrate (12) includes a metal layer (122-130) and an insulating layer (121) connected to the metal layer (122-130). The multiple circuit-breakers (142, 144) are arranged on the metal layer (122-130). The multiple contact elements (182, 184) are also arranged on the metal layer (122-130) such that the multiple contact elements (182, 184) extend perpendicular to a surface of the substrate (12).

Abstract: A power semiconductor device of the present disclosure includes: a first switching element; a second switching element connected in parallel to the first switching element, and having a higher short circuit capability than the first switching element; drive circuits to drive the first switching element and the second switching element; and determination circuits to compare a target current as a sum of a current flowing through the first switching element and a current flowing through the second switching element to a first threshold and a second threshold greater than the first threshold. The drive circuits switch off the first switching element when the determination circuits determine that the target current is equal to or greater than the first threshold, and switch off the second switching element when the determination circuits determine that the target current is equal to or greater than the second threshold.

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Abstract: Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.

Abstract: Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

Abstract: A method of multiplexing control lines of a qubit array includes applying a qubit control signal to a single driveline. The qubit control signal is split on the single driveline between a first resonator and a second resonator. The first driveline is operative to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit by the first resonator. The third qubit is coupled to the fourth tunable qubit by the second resonator. A variation in amplitude of the qubit control signal is compensated by adjusting a frequency of the second tunable qubit and a frequency of the fourth tunable qubit.

Abstract: A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

Abstract: A transistor device includes a transistor and programmable controller. The controller has an output that controls operation of the transistor. The controller includes analog computing circuitry and optionally digital computing circuitry that may be used to setup the analog computing circuitry. In addition to two connectors for connecting the transistor into an external circuit, the device includes a further connector that provides an input to the controller and through which the control can be programmed post manufacture. The transistor device may be a discrete component in which transistor and controlling circuitry are held in packaging, the three connectors exposed through the packaging in order to connect the device to an external circuit.

Abstract: An integrated circuit includes a first stacked transistor switch having a current path coupled between a first tuning element port and a second tuning element port; a second stacked transistor switch having a current path coupled between the first tuning element port and a ground port; and a control circuit coupled to a control node of the first stacked transistor switch and coupled to a control node of the second stacked transistor switch, wherein a series on-resistance of the first stacked transistor switch is greater than a series on-resistance of the second stacked transistor.

Abstract: A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

Abstract: In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

Abstract: Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.

Abstract: According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.

Abstract: The present disclosure provides power semiconductor module, comprising at least three non-jumping power terminals at a non-jumping potential, wherein multiple power semiconductors and at least one first capacitor are integrated within a package and electrically connected between a first non-jumping power terminal and a second non-jumping power terminal of the at least three non-jumping power terminals; and at least one jumping power terminal at a jumping potential. A first jumping power terminal of the at least one jumping power terminal is electrically connected to one terminal of a power inductor and a third non-jumping power terminal of the at least three non-jumping power terminals is electrically connected to the other terminal of the power inductor; wherein at least one second capacitor is electrically connected between the third non-jumping power terminal and at least one of other non-jumping power terminals.

Abstract: According to one embodiment, a semiconductor device includes a first switch element including a first end to which a first voltage is applied, and a second end and a gate electrically coupled to a first node, a second switch element including a first end to which a second voltage is applied, and a second end and a gate electrically coupled to the first node, a third switch element including a first end to which the second voltage is applied, a second end electrically coupled to a second node, and a gate coupled to the first node, a fourth switch element including a gate coupled to the second node, and a first terminal electrically coupled to a first end of the fourth switch element and outputting a signal based on a voltage of the second node.

Abstract: A switch circuit configured to receive power from either a single power source or dual power source. The circuit includes two power input terminals and two power output terminals. For a single power source, the switch circuit may receive the single power source at either of the two power input terminals. The switch circuit provides power to a load without regard to which of the power input terminals the single power source is connected. The switch circuit shorts the power output terminals for a single power input, which provides power at both power output terminals. For a dual power source system, the switch circuit may isolate the two power output terminals so each power output terminal may operate independently without shorting. In some examples, the switch circuit may be part of a thermostat or similar HVAC system controller.