Abstract: According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.

Abstract: Provided is a gate driving apparatus, including: a gate driving unit for driving a gate of a switching device; a switching unit for switching a gate current of the switching device during, within a turn-on period of the switching device, at least a part of the period, which is after timing when a current starts to flow in the switching device, to a smaller current when compared to the gate current before at least a part of the period.

Abstract: Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber. Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch; and a second switch, where a first terminal of the first voltage source is coupled to a first terminal of the first switch, and where a second terminal of the first voltage source is coupled to a first terminal of the second switch. The waveform generator also includes a current stage coupled to a common node between second terminals of the first switch and the second switch, the current stage having a current source and a third switch coupled to the current source.

Abstract: A power device and an electrical appliance are provided. The power device has a control input terminal, a first driving circuit and a second driving circuit. When the control input terminal is connected to a high level or a low level, the first driving circuit and the second driving circuit output a high/low level signal in a first voltage range or a high/low level signal in a second voltage range. The first voltage range is different from the second voltage range.

Abstract: An electronic device includes an electronic component, a driving circuit and a circuit. The driving circuit is electrically connected between a node and a first voltage. The electronic component is electrically connected between the node and a second voltage. The circuit is electrically connected between the node and a third voltage. The first voltage is different from the second voltage and the third voltage.

Abstract: A protective circuit for a semiconductor switch includes a clamp diode, an NPN bipolar transistor, a PNP bipolar transistor, a capacitor connected in parallel with the base-emitter path of the PNP bipolar transistor, and at least three resistors. The bipolar transistors are connected to a thyristor structure that is connected to the cathode of the clamp diode. A first resistor is connected in parallel with the base-emitter path of the NPN bipolar transistor. A first terminal of the second resistor is connected to the base of the PNP bipolar transistor. Either a third resistor is connected in parallel with the base-emitter path of the PNP bipolar transistor, or a first terminal of the third resistor is connected to the emitter of the PNP bipolar transistor and the second terminal of the third resistor is connected to the second terminal of the second resistor.

Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

Abstract: According to some embodiments, a half-bridge circuit is provided. The half-bridge circuit includes a substrate, a monolithic die over the substrate, a switch node, a high-side switch integrated with the monolithic die and coupled to the switch node, and a conductive structure including a first terminal coupled to the substrate and a second terminal coupled to the switch node.

Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.

Abstract: An over-current protection circuit for composite transistor devices is provided, connected between an input terminal and a load, and including: a control-terminal voltage-generation module whose output voltage varies with its input voltage when driven by a first voltage, wherein the output voltage of the control-terminal voltage-generation module serves as a control-terminal voltage; a composite transistor device, connected between the control-terminal voltage-generation module and the load, configured to conduct in response to the control-terminal voltage and a second voltage to generate an output current flowing through the load; and an over-current protection module, connected between the composite transistor device and the load, wherein when the output current of the composite transistor device exceeds a preset limit, a clamping voltage is applied to the composite transistor device by the over-current protection module to limit a current flowing through the composite transistor device, thereby limiting th

Abstract: A digital high-speed hybrid load pull test system comprises a slide screw automatic passive tuner, a digital active forward injection loop in a closed loop transmission configuration, calibration and tuning algorithms. The forward active injection loop comprises at least one adjustable coupler, a digital electronic tuner and feedback power amplifier; the passive tuner comprises one or more metallic tuning probes, used to create passive reflection factors. Small signal calibration of the passive and active tuners create a global calibration data base, used to pre-tune in the area of the target impedance and final high power (nonlinear) tuning employs a in-situ signal power wave search and measurement for digital impedances around the small signal pattern. The system provides for high speed low injected power tuning with maximum reflection factor at DUT reference plane reaching unity.

Abstract: A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: A load drive device includes a semiconductor element and a current detection resistor. The semiconductor element includes a first main electrode provided on a front surface side and having a higher potential and a second main electrode provided on a back surface side opposite to the front surface and having a lower potential than the first main electrode. The second main electrode is divided such that the semiconductor element includes a main element that supplies electric power to a load in response to the main element being turned on and a sense element that detects a current. The current detection resistor is connected in series to the sense element and provided between the second main electrode of the sense element and the second main electrode of the main element.

Abstract: A circuit, intended to be associated in series with a load to be powered including a first field-effect transistor; at least one second field-effect transistor, associated in parallel with the first transistor; and at least one sensor of information representative of a current transmitted to said load, the gate of the second transistor being coupled to an output of the sensor.

Abstract: Apparatus for performing substrate voltage management is provided herein and comprises an active substrate voltage management circuit configured to be coupled to a substrate of a bidirectional gallium nitride high electron mobility transistor comprising a first source and a second source. The active substrate voltage management circuit comprises a first circuit that is connected to the first source and a second circuit that is connected to a second source such that when the bidirectional gallium nitride high electron mobility transistor is operational one of the first circuit or the second circuit connects one of the first source to the substrate or the second source to the substrate, respectively, to control a bias voltage applied to the substrate.

Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

Abstract: An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.

Abstract: The present disclosure discloses an anti-backflow output switch, a collector of the tertiary tube Q6 is connected to the source of the MOS tube Q4 through a resistor R24 and a diode ZD2, a resistor R30 is connected between the source and the gate of the MOS tube Q4, the drain of the MOS tube Q4 is connected to the drain of the MOS tube Q9, a resistor R25 and a diode D5 are connected to the gate of the MOS tube Q9, a resistor R28 is connected between the gate and the source of the MOS tube Q9, a resistor R33 is connected between the drain of the MOS tube Q10, a resistor R37 is connected between the gate and the source of the MOS tube Q10, the gate of the MOS tube Q10 is connected to a first pin of the chip U2 through a resistor R35, a resistor R34 and a resistor R38 are connected to the second pin and the third pin of the chip U2 respectively, a resistor R39 and a capacitor C35 are connected between the first pin and the second pin of the chip U2, the second pin of the chip U2 is connected to a fourth pin of t

Abstract: A real-time clock device includes a package that houses a resonator, an oscillation circuit, a clocking circuit, and a functional circuit, and on which external terminals are formed.

Abstract: An electromagnetic interference regulator by use of capacitive parameters of the field-effect transistor for detecting the induced voltage and the induced current of the field-effect transistor to determine whether the operating frequency of the field-effect transistor is within the preset special management frequency of electromagnetic interference. When the basic frequency and the multiplied frequency exceed the limit, the content of the external capacitor unit can be adjusted to assist the products using field-effect transistors to maintain excellent electromagnetic interference adjustment capabilities under various loads, thereby optimizing the characteristics of electromagnetic interference.