Abstract: A plurality of slide access memories (SM.sub.00, SM.sub.01, . . . , SM.sub.n-1, m-1), in which a voluntary rectangular group of bits can be accessed, are arranged in an n-rows and m-columns matrix and connected to common data lines (D.sub.0, D.sub.1, . . . , D.sub.15). A first access means accesses the same rectangular group of bits in each of the slide access memories and interconnects these groups to input/output portions incorporated into each of the slide access memories. A second access means selects the input/output portions of each of the slide access memories to enable or disable the operation thereof in accordance with a special bit position, or a pointing bit (PB) position, to thereby connect only a desired group of bits to common data lines, and thus enlarge the scope of slide access memories.

Abstract: A semiconductor memory device includes a first memory cell array and a second memory cell array section into which the same data can be simultaneously written. Logic gates are provided between the word lines of the first memory cell array section and the respective word lines of the second memory cell array section. In the normal operation mode, the logic gates connect each of the rows of memory cells in the first memory cell array section to a corresponding one of the rows of memory cells in the second memory cell array section, and set each of the rows of memory cells in the second memory cell array section to a selected level when the same data is simultaneously written into the memory cells of the second memory cell array section.

Abstract: A data storage device includes two registers associated with each cell of the memory. The first register forms a read/write memory register, and the second register forms a write-only shadow register connected to the memory register. During normal operations, each memory register operates as an independent random access memory (RAM) cell and each shadow register operates as an independent write-only RAM cell. When data is written to a shadow register, a flag bit is set. Subsequently, a validity check may be performed to verify the data. If the data does not verify, a clear line may be used to clear the flag bits. If the data verifies, the data in each shadow register with a flag bit set can be loaded into its corresponding memory register in a gang loading operation. If a shadow register flag bit is not set, the data in its corresponding memory register is not changed during gang loading.

Abstract: An electrically erasable programmable read only memory (EEPROM) latches externally applied write data in column latches, erases information of selected memory cells and then writes the latched write data into the selected memory cells. This EEPROM includes detectors for detecting a potential of the latch node of the corresponding latch, chargers each for charging the corresponding bit line in response to the output of the potential detector in a latched data write cycle, and separation transistors each for separating a bit line from the latch node of the corresponding column latch in response to the activation of the chargers.

Abstract: A dynamic random access memory system comprising a memory cell matrix, a row address decoder connected to the memory matrix and a counter for producing internal address signals to refresh the cells of the memory cell matrix. A row address buffer converts the external address signals to row address signals in response to an address buffer enabling signal, and a switching circuit connected to the counter and the row address buffer is selectively switching between the counter and the row address buffer in response to an address switching signal. A decoder circuit connected to the output of the switching circuit decodes selected address signals and provides decoded address signals to the row address decoder.

Abstract: A static random access memory (RAM) circuit arranged such that the data stored in a memory cell is readout by detecting a transition address signal level. That is, an address transition pulse is generated by detecting an address signal transition, and first and second pulses are generated by detecting a starting edge and a trailing edge of the address transition pulse respectively. The first pulse enables a selected word line for reading out the data stored in selected memory cells. The second pulse enables an data output circuit coupled to the bit lines for transferring the readout data to an output terminal. Under such an arrangement, memory access operation becomes faster, and even if "skew" phenomenon is caused, the transient data readout from the memory cells instantaneously is prevented from being transferred to the output terminal.

Abstract: There is disclosed a dynamic random access memory device of the type capable of periodic self-refresh cycles of operation. The DRAM includes the detector circuit for detecting the designation of the self-refresh mode and a voltage generator circuit for generating a voltage to precharge the bit line pair. During the self-controlled refresh cycle, the bit line pair is equalized and precharged to a voltage lower than Vcc/2. When it is attempted to set the time interval between the self-refresh cycles in order to reduce current consumption, the level of voltage stored in the memory cell capacitor tends to decrease due to charge leakage. However, it is implemented to provide and keep a potential difference between the precharge voltage on the bit line pair and the voltage stored in the capacitor thereby to secure the desired sensing margin for the sense amplifier.

Abstract: A read-only memory incorporated on a single substrate for use with a microprocessor system is described. The memory includes a transceiver for passing data and first address signals, and the transceiver has a first side for coupling to a first plurality of lines. A first latch for latching the first address signals is provided, wherein the first latch has a first side coupled to a second side of the transceiver. A first buffer is provided, the first buffer having a first side coupled to a second side of the first latch. A second buffer for buffering second address signals is provided, the second buffer having a first side for coupling to a second plurality of lines. A second latch for latching the second address signals is provided, wherein the second latch has a first side coupled to a second side of the second buffer. A third buffer is provided, and the third buffer has a first side coupled to a second side of the second latch. A memory array for storing the data is further provided.

Abstract: A ferroelectric memory cell has one capacitor isolated from bit lines by two transistors, one on each side. The cell is read by pulsing the capacitor in one direction, then the other, storing developed charge on other capacitors or the like, and comparing voltages.