Abstract: A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: A store through cache environment managed exclusively grants exclusivity on a large granularity basis. A cross-invalidate is realized for all changed lines via a single transmission when exclusivity is released. A dynamic table that operates in conjunction with a directory look-aside table (DLAT) determines a number of pages that can be held exclusive simultaneously. For adequate operating speed, the special table must be either fully associative or at least set associative. Alternatively, the table can be incorporated into the DLAT. Each DLAT entry is also extended to include a set of "resident" bits and a "valid nonresident" bit. When exclusively is released, the set of local change bits is broadcast to all processors. Upon receipt of such broadcast, the appropriate action is to change the "valid nonresident" indication to read-only and to clear residence bits whose corresponding local change bit is set.

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: An address translation system for converting into a real address a virtual address including a virtual section number, a virtual area number and a virtual page number, comprises a plurality of stages of tables including at least area tables and page tables, a translation look-aside buffer having a plurality of entries each storing a virtual section number, a virtual area number and a virtual page number, an area preservation register for preserving a virtual section number and a virtual area number of a given virtual address when a new entry is registered into the translation look-aside buffer, a table register for preserving an output of an area table selected when the new entry is registered into the translation look-aside buffer, and an area comparator for comparing a content of the area preservation register with a virtual section number and a virtual area number of a given virtual address.

Abstract: A computer system and method for operating a computer system capable of running in mutually incompatible real and protected addressing modes, in which programs written for one mode can be run in the other mode without modification. The BIOS assembles two different common data areas for the two modes, each inclusive of device block pointers, function transfer table pointers, data pointers, and function pointers. The common data area for the real mode is assembled first. To assembly the pointers for the protected mode common data area, the offset values from the real mode area ae copied directly, and then selector values are inserted whose physical addresses correspond to the segments of the corresponding pointers in the real mode area. The selector values are derived from a segment descriptor table.

Abstract: A multi-port memory cell utilizes a storage cell to define complementary data storage nodes. Each read port of the memory cell includes two FETs respectively coupled between one of a pair of complementary data-out lines and a read enable line to isolate the read ports. Each of the gates of the two read port FETs is connected to one of the corresponding data storage nodes. The storage cell is read by pulling current from the read enable line and monitoring the difference between the complementary data-out lines.

Abstract: A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM.

Abstract: An address generator that provides equivalent time sampling for a time domain reflectometer generates read and write addesses for simultaneous application to an aquisition memory over an address bus. For each iteration of a repetitive input signal an excitation pulse is delayed by an amount, dt, that is an integer submultiple of a sampling period, T. Read addresses for each iteration of the repetitive input signal start from an initial address and increment by T/dt for each data sample. Corresponding write addresses are generated from the read addresses one sample time later so that the address on the address bus has a read address that is one address ahead of the write address. The acquisition memory reads out data from the read address for accumulation with corresponding sampled data while accumulated data is being input to the write address.

Abstract: An optical storage device having a mass storage medium which remains stationary as data is transferred by a laser. The stationary mass storage medium permits rapid data transfer since delay due to rotation of the medium, as in a compact disk, is eliminated.

Abstract: A material processing system comprising a plurality of peripheral modules and a base module, the base module including a central processor, each of the peripheral modules including a peripheral processor, a serial data link interconnecting each of the processors in a serial manner, the central processor including means for providing a system command signal along the serial link to the first of the peripheral module processors, each the peripheral processor including means responsive to the system command signal for adding thereto a tag, the tag including data representative of the address and configuration of the module, and for passing the system command signal to the next successive module processor, and means for passing the system command signals and tags appended thereto to the base module central processor, the base module central processor including storage means for storing the address and designation data of each the module.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: A data processing unit accesses data in a cache using a virtual address. If the data is not in the cache, the virtual address is translated by a memory management unit (MMU) into a physical address for accessing a main memory. The MMU can also access the cache, using the physical address, to retrieve page table entries held in the cache. This avoids the need for a main memory access to retrieve the page table entries, and hence speeds up the address translation operation. The physically addressed entries in the cache are tagged with a reserved context number to distinguish them from the virtually addressed data.

Abstract: A method and system are provided for updating the software used in remote computer systems from a central computer system. The method includes storing in the central computer system, copies of the software executable used in each remote computer system. When the copies of the software in the central computer system are upgraded, for example, to correct the software, to add new facilities, to change user interfaces, to make cosmetic changes, to improve performance, etc., each change made to the software is monitored and stored. The remote computer systems are permitted access to the central computer system via communication links and the software in the remote computer systems and the corresponding software in the central computer system are compared. All of the changes that have been made to the software at the central computer system which have not been made to the corresponding software at the remote computer system accessing the central computer are detected.

Abstract: A replacement method is provided for improving the hit rate and testability of a page address translation cache (PATC). The replacement scheme uses a modified FIFO replacement algorithm. A circular shift register has a pointer which points to each of a predetermined number of translation descriptors stored in the PATC. The shift register pointer has an input for receiving the logic state of a valid bit associated with each of the translation descriptors stored in the PATC. The shift register is advanced after every translation cycle, until the logic state of the valid bit indicates that the denoted translation descriptor is invalid, or until a read/write control signal indicates a PATC write is in progress. Upon detecting an invalid translation descriptor, the circular shift register is disabled, and remains disabled until an address translation "miss" occurs, and a replacement entry is loaded into the PATC. If, however, an address translation miss occurs while the circular shift register is enabled (i.e.

Abstract: In a pipeline data processing system, a method for additively converting an address expressed in offset form to a corresponding real address in main memory (assuming that such address exists in main memory). Because of the pipeline data processing design, this offset address can be accessed from main memory in the same amount of time required by a non-offset, real address. An apparatus for practicing this method is also provided. This method and apparatus will perform the functions usually performed by a translation table or similar device in virtual memory systems. Furthermore, it will perform those functions faster and will utilize a smaller integrated circuit area than translation table type virtual memory systems.

Abstract: An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or same as an UV-EPROM. Erasure operating is performed by applying negative voltage to a control gate so as to inject holes into the floating gate.

Abstract: A nonvolatile memory has integrated memory cells each operative to carry out writing and reading of information on a random-access basis and each having an electric charge storage structure effective to memorize the information in a nonvolatile state. The information is temporarily written into each memory cell in a volatile state, and thereafter the temporarily written information is written at once into a respective electric charge storage structure of each memory cell, thereby effecting high speed writing of nonvolatile information into the respective memory cells.

Abstract: In a multiprocessor computer system, a number of processors are coupled to main memory by a shared memory bus, and one or more of the processors have a two level direct mapped cache memory. When any one processor updates data in a shared portion of the address space, a cache check request signal is transmitted on the shared data bus, which enables all the cache memories to update their contents if necessary. Since both caches are direct mapped, each line of data stored in the first cache is also stored in one of the blocks in the second cache. Each cache has control logic for determining when a specified address location is stored in one of its lines or blocks. To avoid spurious accesses to the first level cache when a cache check is performed, the second cache has a special table which stores a pointer for each line in said first cache array. This pointer denotes the block in the second cache which stores the same data as is stored in the corresponding line of the first cache.

Abstract: On generating a logical address from first through third words where the third word has a predetermined word length and the first and the second words are longer, a lower sum is calculated together with a carry by using the third word and first and second lower parts which are selected from the first and the second words to have predetermined word length. The carry is either a binary zero or a binary one bit. Necessity or lack of necessity for addition of first and second higher parts and the carry is decided by using the second higher part and the carry. When the addition is unnecessary, the first higher part and the lower sum are concatenated into the logical address. If the addition is necessary, a higher sum of the first and second higher parts and the carry is calculated and concentrated with the lower sum into the logical address.

Abstract: A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.