Abstract: Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

Abstract: An electrically programmable non-volatile memory comprises an array of word lines (LM2) extending along rows, connecting the control gates of floating gate transistors, and an array of bit lines (LB1, LB2) extending along columns, connecting the drains of the floating gate transistors. A conductive area (35) having a larger size than each floating gate (23) along horizontal direction, is connected to the floating gate (23) of each transistor, and is superposed with the corresponding word line (LM2) from which it is separated by an isolation layer (28).

Abstract: An asynchronous semiconductor memory operates to detect transition of address to thereby generate a clock. A skew time period can be varied from the transition of an address signal to the generation of an internal clock.

Abstract: The invention relates to a bit line precharge circuit of a multi-sectional memory array in which a first set of circuits gate a section decoding signal and a main bit line precharge pulse and a second set of circuits gate the section decoding signal and a main data line precharge pulse. The resultant signals from the first and second sets of circuits are fed into respective inverter circuits and then respectively into a bit line precharge circuit and a data line precharge circuit so that the operation margin of the section decoding signal increases by as much as the width of the main bit line precharge pulse.

Abstract: This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

Abstract: A column decoder is driven by an intermediate potential VDD from a circuit for generating an intermediate potential between a Vcc potential and a Vss potential, and a column selection output having a swing width of the intermediate potential is supplied to the gates of column selection transistors to limit a current flowing therethrough. In the data readout mode, a precharge potential generated from a dummy cell circuit acting as a reference potential generating circuit according to a precharging signal supplied thereto is compared with a logic level of "1" or "0" read out according to the memory content by means of a flip-flop acting as a sense amplifier, thus deriving a data readout output.

Abstract: A method and apparatus for a Surface-Enhanced Raman Optical Data Storage (SERODS) System is disclosed. A medium which exhibits the Surface Enhanced Raman Scattering (SERS) phenomenon has data written onto its surface of microenvironment by means of a write-on procedure which disturbs the surface or microenvironment of the medium and results in the medium having a changed SERS emission when excited. The write-on procedure is controlled by a signal that corresponds to the data to be stored so that the disturbed regions on the storage device (e.g., disk) represent the data. After the data is written onto the storage device it is read by exciting the surface of the storage device with an appropriate radiation source and detecting changes in the SERS emission to produce a detection signal. The data is then reproduced from the detection signal.

Abstract: A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits for latching data in response to first and second latch control signals, respectively, a first data transfer gate connected between the first circuit and the first latch circuit and responsive to a first gate control signal to make electrical connection or disconnection therebetween, a second transfer gate connected between the first and second data latch circuits and responsive to a second gate control signal to make electrical connection or disconnection therebetween, and a third data transfer gate connected between the second data latch circuit and the second circuit and responsive to a third gate control signal to make electrical connection or disconnection therebetween.

Abstract: The present invention relates to a memory cell, and more particularly to a single-bit, dual-port cell, and a single-sided read circuit for use with one or more such cells. The cell may, in one embodiment, be used in a static random access memory (RAM) array, and may be implemented in BICMOS technology on an integrated circuit. The cell has a flip-flop storage unit comprising a CMOS circuit of cross-coupled inverters coupled to dual CMOS pass gates to provide isolation and data transfer. The storage unit is also coupled to a bipolar read line driver in a particular configuration to accomplish rapid bit line pull-up or pulldown for high speed read operation. Several alternative embodiments are disclosed.

Abstract: A semiconductor associative memory device comprises a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line. The memory cell comprises first and second n channel MOS transistors constituting a capacitance element. When the word line is activated, a value on the bit line is stored in the first n channel MOS transistor, and the value on the inversion bit line is stored in the second n channel MOS transistor. When the first n channel MOS transistor and the bit line are in the active state, or when the second n channel MOS transistor and the inversion bit line are in the active state, a control terminal is activated. N channel MOS transistors are connected between the control terminal and the first and second n channel MOS transistors, and the first and second n channel MOS transistors are refreshed during matching and reading by means of these transistors.

Abstract: A dynamic random access memory includes a dummy word line which has an electrical characteristic identical to that of an actual word line. The dummy word line is charged up and is then discharged as in case of the actual word line. A latched row address in a row address latch circuit is reset when the potential of the dummy word line becomes equal to a predetermined low potential due to the discharge operation for the dummy word line.

Abstract: In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet formed below the input gate. In order to eliminate this fluctuation and hence to increase the permitted interference margin for other interference sources, a voltage stabilization circuit is arranged between the supply voltage and the input gate so that the fluctuation in the supply also occurs at the source zone, as a result of which the size of the charge packet becomes independent of the supply. For the voltage stabilization circuit, use may advantageously be made of a band gap reference.

Abstract: Asymmetrical delay circuitry comprising a chain of inverters connected to logic gates is disclosed which can be implemented at the word line driver or in the address decode circuitry of a memory.

Abstract: A semiconductor memory device comprises first and second dummy memory cells. The first dummy memory cell is connected between a normal row line and a dummy column line. The second dummy memory cell is connected to a dummy row line and the dummy column line. The dummy row line is applied with an output voltage of a bias circuit which applies a constant voltage. The second dummy memory cell is used as a reference memory cell and generates a reference potential which is kept unchanged.

Abstract: The present invention relates to a method for arranging a read memory for reading electrically updating status information from an integrated circuit (3) which comprises various circuit layers. Patterned circuit layers, so-called pattern layers, are produced, for instance, from a respective mask which has been made particularly for each of the pattern layers. According to the invention, each pattern layer in which reconstruction can be made has provided therein a separate memory device, such that when changes are made in one such pattern, the updating status of the pattern layer can be written into the memory device in code form. The memory devices included in an integrated circuit form a read-only-memory which is programmed so that the pattern layers in which a memory device is provided contain a code which is individual to its own updating status. At the same time as the updating status code is written into the memory device, the code is also written into a test device (2) as reference information.

Abstract: A semiconductor memory device includes an array of memory cells arranged in rows and columns, a plurality of divided bit line pairs connecting the memory cells, the divided bit line pairs extending along a given column of memory cells, and a pair of main bit lines extending substantially parallel to the divided bit line pairs. The semiconductor memory device further comprises a plurality of sense amplifiers, each provided for two adjacent divided bit line pairs, a plurality of first switching circuit, each of which is provided for connecting each sense amplifier to either of the two adjacent divided bit line pairs, and a plurality of second switching circuit for transferring the output signal of each the sense amplifier to the pair of main bit lines.

Abstract: A DRAM controller wherein the outputs of a 74F538 integrated circuit provides RAS signals to the banks of a DRAM array, respectively, where the 74F538 is located at the array. A microprocessor utilizing the array provides appropriate memory address signals, a refresh request signal and a RAS timing signal. A PAL16L8B responsive to the memory address, refresh request signal and RAS timing signal encodes the memory address into a digital RAS signal having fewer bits than the number of memory banks. The digital RAS signal represents the selected bank for a memory access cycle. The digital RAS signal is conveyed in parallel on a bus coupling the PAL to the 538. The PAL generates an enable signal in response to the RAS timing signal to enable the 538 during memory access cycles. During memory access cycles, the 538 decodes the digital RAS signal to enable one of the outputs thereof in accordance therewith.

Abstract: An amplitude limiting circuit is arranged in a DRAM with (1/2) VCC precharge to equalize an amplitude between a precharge voltage and an "H" level output of each pair of bit lines charged and discharged in an active cycle with an amplitude of the precharge voltage and an "L" level output of each pair of bit lines.

Abstract: The disclosure concerns electrically programmable memories and, notably, the memories known as EPROMs, EEPROMs, FLASH-EEPROMs. To increase the information storage capacity of a memory, it is proposed to define at least three (instead of two) sections of current coming from a cell to which reading voltages are applied. These sections correspond to n possible programmed states of the cell. Comparators define a piece of information stored, for example, in two-bit form on the outputs S1, S2. However, to ensure safety during the reading despite programming uncertainties, the cell is tested by means of additional comparators and, if the cell current measured for a programming level defined among n levels is too close to the current threshold that defines the programming threshold at this level, an operation for complementary programming of the cell is triggered.

Abstract: A sense circuit incorporated in a semiconductor memory device has a conduction path between a specified non-volatile memory cell and a source of constant voltage level for deciding the logic level of the data bit read out form the memory cell, and the conduction path is divided into a plurality of channels formed in field effect transistors arranged in parallel and different in threshold voltage for improving an access time without sacrifice of a low sensitivity to noises, so that the conduction path is increased in current driving capability, thereby allowing a parasitic capacitance to rapidly be charged up.