Abstract: Same test data is written into corresponding memory cells of each subarray of a memory cell array to be read out. A comparing and determining circuit determines whether the data read out from each memory cell has the same logic or not, and the data proves defective when any one of the data has different logic. An output of the comparing and determining circuit is stored in a register to be externally outputted through a predetermined pin (e.g. output enable pin). Timing in which the register accepts the data stored in the comparing and determining circuit is controlled by a switching controlling signal generating circuit disposed in a semiconductor memory device. As the above, all signals necessary for a test are generated in the semiconductor memory device, and the test result is outputted through an existing pin, so that it is structured by the same number of pins as that of a standard semiconductor memory device without a testing function.

Abstract: Method and apparatus for storing digital information in a dense memory structure. A semiconductor substrate has a thin insulating layer formed thereon. Over the thin insulating layer is formed a dielectric charge-storage layer. A piezoelectric bimorph cantilever arm has a tip formed at its free end to access certain memory sites defined by charge-storage regions in the charge-storage layer. To write infromation in the form of charges into a memory site the tip contacts or is in close proximity to the surface of the charge-storage layer and an electric field is applied between the tip and the substrate to induce charges to tunnel through the thin insulating layer into the charge-storage layer where the charges are stored as trapped charges. Information is read from a storage-site by spacing the tip of the cantilever arm a distance from the surface of the charge storage layer and applying an electric field between the tip and the substrate.

Abstract: A caching memory system including a translation look-aside buffer having a preselected number of lines of memory, each of said lines including storage for a virtual address and a physical address, apparatus for selectively varying the size of pages the virtual and physical addresses of which may be stored in the translation look-aside buffer, and apparatus for interrogating the virtual addresses to determine whether a requested address is stored in the translation look-aside buffer.

Abstract: A memory system includes a memory unit with plural addressable storage locations, a connector arrangement for detachably electrically coupling the memory unit to a computer, and a decoding arrangement for determining whether a computer memory address is within a range of addresses to which the memory unit is to respond, the decoding arrangement including a base address register storing a value representing the first address in the range and a size register defining the number of addresses in the range.

Abstract: In a system including a main body for processing data and a memory detachably provided to the main body, an addressing method for addressing the memory to write data therein or to read data therefrom being that plural bits of an address to be applied to the memory from the main body are divided into two parts, one part of address bits is transmitted to the memory through an address line provided for addressing the memory while another part of address bits is transmitted to the memory through a data line provided for communicating data between the main body and the memory, and two parts of address bits are joined in the memory to access the memory by full bits of the address.

Abstract: A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.

Abstract: A virtual memory management cache memory system has a plurality of directory and buffer store levels for storing page descriptor information. The cache memory directories and a least recently used (LRU) apparatus for replacing information within the buffer store on a least recently used basis are constructed from the same type of standard cache address directory part. Programmable control circuits generate the required input data and control signals which are applied to the LRU apparatus for obtaining signals which indicate a next level to be replaced on a least recently used basis and for updating the contents of the LRU apparatus on a most recently used basis.

Abstract: A dynamic random access memory including a memory cell array, an address supply part, a data input/output part and a word line driver. The word line driver increases word lines to a first voltage during a first predetermined period after a first timing when the address supply circuit selects one of the word lines for reading out data and a second predetermined period after a second timing when the address supply circuit releases the one of the word lines from a selected state and maintains the one of the word lines at a second voltage less than the first voltage during an interval between the first and second predetermined periods.

Abstract: Variable length data stored in a RAM are sequentially read out by designating their addresses. It is detected whether or not the readout data is a code indicating a delimitation of, e.g., a word block, record block, file block, or the like. If it is detected that the readout data is a code indicating a delimitation, an address at that time is latched, thus forming an address table based on the latched address. The address table thus formed is utilized upon retrieval of data in the RAM, thus allowing high-speed data access.

Abstract: Each of memory cells in a nonvolatile content-addressable memory (CAM) comprises a first memory transistor connected to a first storage node, a second memory transistor connected to a second storage node, and a memory capacitor connected between said first and second storage nodes. The first storage node is connected to a first bit line through an MOS transistor, and the second storage node is connected to a second bit line through the MOS transistor. In addition, each of the memory cells has a function of determining whether or not information applied to the first and second bit lines and information applied to the first and second storage nodes match with each other. In the nonvolatile CAM, writing and reading by a DRAM operation become possible by using the memory capacitor in each of the memory cells. In addition, in the nonvolatile CAM, nonvolatile writing and reading by an EEPROM operation become possible by using the first and second memory transistors in each of the memory cells.

Abstract: A least recently used associative map is described for translating virtual memory addresses to real memory addresses. The map includes a stack of storage devices each with a comparator. The storage devices are arranged in a push down stack with an input storage device to receive the incoming virtual address and store the corresponding real address and the other storage devices coupled to the output of the previous higher storage devices and with storage devices storing the translation of virtual address and real address in order of recent use with the last or bottom storage device storing the least recently used device. When the comparator detects a compare that real address is provided out and that translation is applied to the input storage device as the most recently used translation and the other translations are shifted down the stack to replace in the storage device that had the compare with the translation from the previous storage device.

Abstract: A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.

Abstract: A memory cell array includes data storing memory cells which are arranged in a matrix form of m rows.times.n columns. The data storing memory cells are selected by means of m word lines and n bit lines. Dummy capacitance cells are arranged on the (n+1)th column of the memory cell array, and are connected to the word lines. The dummy capacitance cells are each formed of a transistor which has the same construction as a field transistor having a gate electrode formed of a polysilicon layer or the data storing memory cell and whose source is set in the electrically floating condition. Array edge memory cells are arranged on the (m+1)th row of the memory cell array, and are connected to n bit lines. The array edge memory cells have no influence on the circuit operation. A dummy memory cell is arranged in an intersecting position of the (m+1)th row and the (n+1)th column.

Abstract: In an access control device (30) for use in combination with first through (2.times.m)-th memory units (m: 2, 3, . . . ) each of which is assigned with at least one of addresses consecutively numbered among the memory units, each of first through m-th arithmetic circuits products, in response to a base address B of the addresses and a preselected distance D, an arithmetic result (B+nD), where n represents one of first through m-th values which are equal to "0", "1", . . . , and "m-1", respectively. A value distributing circuit (36) is preliminarily given the values and distributes the first through the m-th values in response to a distributing control signal. Responsive to the base address and to the preselected distance, a signal producing circuit (39) produces the distributing control signal. A result distributing circuit (43) distributes the arithmetic results of the first through the m-th arithmetic circuits to the first through the (2.times.m)-th memory units as selected ones of the addresses.

Abstract: A virtual memory nmanagement system and method in which the mechanism for selecting the pages to be swapped out of a process's working set takes into account special criteria for swapping out page table pages. When all the virtual memory pages referenced by a page table page are invalid, but some remain stored in primary memory, the page table page becomes eligible for removal from the process's working set. A page table page is made eligible for being swapped out to secondary memory only when every virtual memory page referenced by that page table page is invalid and no longer stored in primary memory.

Abstract: A processor having a memory for use as a stack and a stackpointer provided within the processor, includes circuits for judging a underflow and a overflow of the memory by receiving address of the stackpointer and a signal showing a stack operating instruction from an instruction decoding part in the processor, so as to be capable of calling a subroutine at a high speed, and judging and preventing an overflow or underflow of the stack.

Abstract: A system providing a guess mechanism for improving the speed of translating effective addresses produced by a processor to real addresses in memory is disclosed wherein a set of Lookaside Tables and logic elements are used along with a set of validity registers and an MRU register to guess at the appropriate real frame index from one of the Tables to be output in the real address in the first cycle of a two cycle operation. The low order bits of the effective address are sent to index the Tables during the first cycle and the high order bits are used during the second cycle for comparison with the set of Table entries selected in the first cycle as containing the real frame index that is output. The selection of the actual real frame index that is output involves a guess using the validity and MRU registers along with indexing of the Tables by a portion of the low order bits.

Abstract: A memory cell array includes static memory cells arranged in an array of n rows.times.m columns. Each of the memory cells includes MOS transistors formed in a semicondutor substrate and in a corresponding one of well regions of the conductivity type opposite to that of the semiconductor substrate. The well regions are independently formed for each row or for every two or more rows of the memory cell array. The well regions are connected to the respective sources of MOS transistors formed in the well regions. The source and backgate of each of the MOS transistors formed in the well regions are connected to the common source wirings for each of the independently formed well regions. Isolation circuits are respectively connected between the common source wirings for the repective well regions and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.

Abstract: The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each row of memory cells. The added transistor is a positive voltage threshold device which is coupled between the connected sources of the floating gate transistors and a read input line to limit the threshold voltage. For programming, a second transistor with a negative voltage threshold is coupled in the same manner, but is coupled to a program input line. The positive threshold transistor prevents an unselected transistor from turning on during a read operation.

Abstract: A computer memory is transformed such that a data word to be sent to an address is transformed into a transformed data word, and the address to which it is to be sent is transformed to a transformed address. Such transformations are by inversion and permutation of the memory lines (address or data). The data transformation process depends on the address. The data inverse transformation process also depends on the address, but there is no address inverse transformation process. The invention may be used whenever it is desired to more nearly equalize the use of all the bits of the memory, or to impede unauthorized persons from extracting the virtual addresses and data from the transformed addresses and data.