Abstract: A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed.

Abstract: A content-addressed memory system stores large amounts of data for quick access by keyword value combinations. The system comprises a controller and a plurality of content-addressed memory chips. Each chip comprises a plurality of word cells with logic to enable independent, parallel operation of each word cell, storage of a record of closely related data in more than one word cell, and accessing an entire record when data in one word cell is matched to the keyword value.

Abstract: A current differential sense amplifier for static RAM cells which couple one of a pair of bit lines to a current source for a high speed read operation. The sense amplifier has current mirrors which amplify the current on each of the bit lines. The amplified currents are fed into an active load which has an output node which rises and falls in voltage depending upon the current mismatch. An inverter connected to the output node speeds the slow rate of the node.

Abstract: A flash EPROM memory array having vertical blocking is described. The array is organized into a plurality of vertical (column) blocks. Each block includes a source region switch which couples all the source regions in the memory cells in its respective block to a programming potential, ground or a disturb inhibit potential. Each of the blocks may be erased without disturbing the programming in the other blocks.

Abstract: A dynamic random access memory, which includes a data input buffer, a data input latch circuit, a data output buffer, and a switching circuit. For example, in an operation in a read-write cycle, at first, a data signal to be written is stored in the latch circuit 7 concurrent with inputting of an address signal in response to a signal WE. A data signal read from a memory cell is output via the output buffer in response to a signal OE. The switching circuit is turned on, and the data signal which has been latched is provided to the memory cell via a pair of I/O lines. As a result, the time required for the operation in the read-write cycle is shortened.

Abstract: A nonvolatile memory device has a memory cell having its gate connected to a word line, its source connected to a ground potential and its drain connected to a power supply voltage via a bit line and a dummy cell having its gate connected to the word line, its source connected to the source potential and its drain connected to the power supply voltage via a dummy bit line. The bit line and the dummy bit line are connected to reset and set terminals of a sense amplifier circuit comprising a flip-flop circuit and a latch type of sense amplifier. The conductance of the dummy cell is made smaller than that of the memory cell so that the speed at which the potential on the bit line is lowered depends on the state of injection of electrons into the memory cell as compared with the speed at which the potential on the dummy bit line at a time of reading data.

Abstract: The invention provides an improved semiconductor memory device such as a static RAM. The semiconductor memory device attains high speed read-out of data therefrom without increasing a step of production process. The semiconductor memory device further attains a flash-clearing function without increasing the size of a chip thereof.

Abstract: In a static RAM having an internal low voltage transformation circuit, a word line drive circuit is provided which applies a low voltage, from an internal low voltage transformation circuit to a word line during read-out to improve the static RAM operating margin. The internal low voltage transformation circuit is formed by a reference voltage supply circuit and an internal voltage control circuit. A data hold voltage is supplied, when the static RAM is operating at a lower voltage, by a power pull-down device having a lower power consumption than the internal low voltage transformation circuit so as to achieve power consumption savings.

Abstract: A circuit arrangement comprising, for each bit location in a column of a RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into a bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit. The result is stored in the shift register, which can be down-loaded for analysis.

Abstract: An associative memory for storing an n-bit stored vector in m different states comprises n first amplifiers connected between n input terminals and n output terminals, and m second amplifiers to feedback to the input side the designated states of the stored vectors. Synapses of the storing unit store the above mentioned stored vectors in the a binary 1 or 0; synapses of the label units couple the respective intersections between the input and output lines of the second amplifiers; and synapses of the vector units couple the intersections between the output lines of the first amplifiers and the input lines of the second amplifiers. According to the present invention, the outputs of the amplifiers are stabilized, so that stabilized operations can be obtained.

Abstract: A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.

Abstract: A first-in, first-out, memory has a random access memory (RAM) for storing a plurality of information words seriatim. The use of such memory is significantly enhanced by arranging the memory so that it calculates and outputs to respective terminals the number of RAM locations which contain information words and the number of RAM locations which are empty. Each number is outputted responsive to receipt of a respective request to do so.

Abstract: A semiconductor integrated circuit device includes a pulse width expander circuit for expanding the pulse width of a pulse signal of the ECL (emitter coupled logic) level that has a very narrow pulse width, a level conversion circuit for converting the output signal of the ECL level of the pulse width expander circuit into a CMOS (complementary metal oxide semiconductor) level, and an internal circuit that is so connected as to receive the output signal of the level conversion circuit. In other words, the pulse signal having a narrow pulse width is expanded to have a pulse width which is sufficient for the level conversion circuit prior to performing the level conversion operation. Therefore, the level of the pulse signals having narrow pulse widths is stably converted.

Abstract: An input/output circuit wherein a plurality of data lines are provided with a serial/parallel conversion means common to all, so that the circuit is enabled to consume less power and draw a reduced instantaneous current in its operation and be fabricated in an integrated circuit form.

Abstract: A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.

Abstract: A read-only memory for storing a plurality of bits of information. The read-only memory includes a plurality of memory cells arranged in an array with each memory cell including a capacitor having either a relatively high capacitance or a relatively low capacitance representing a bit of stored information. The read-only memory further includes a reading means for accessing each memory cell and providing a first or second output responsive to the capacitance level of the memory cell capacitance means.

Abstract: A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the respective PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing a selected one of the first or second PNP transistors into an active mode of operation.

Abstract: A timing circuit is described for a single phase clocked memory. The output of a flip-flop is used to initiate the generation of a plurality of control signals through models of circuit elements of the memory such as the word line, bit line, etc. The output of these models are used to generate control signals both when the flip-flop is set and reset. The flip-flop is reset by a signal from one of the models.

Abstract: A static random access memory (SRAM) comprises plural memory cells, a true-bit load and a complementary-bit load, a true-bit line and a complementary bit line, a sense amplifier and an address transition detector. The address transition detector is used to generate load pulses which switch off the loads just after either of the memory cells is selected. This speeds signal development during a read (or write) operation. Since provision is made for modulating the loads, they can be designed to permit larger-than-conventional currents to flow therethrough when maximally on. The loads are maximally on just after cell deselection to facilitate bit-line equalization between cell selections. Thus, the present invention provides for briefer inter-select periods, quicker reads upon cell selection, and, thus, a faster SRAM overall.

Abstract: A testing circuit for a semiconductor memory device is provided. An AND operation is performed on the data read out from each block of a memory cell array when the bit data written into each block of the memory cell array for testing is "1", and a NOR operation is performed on the data read out from each block of the memory cell array when the bit data written into each block of the memory cell array is "0". In this manner, even when the data read out from the blocks are all inverted in their logical states through error, such error can be detected.