Abstract: Embodiments of the present disclosure are directed to a side-gated fin field effect transistor configured as a scanning single electron transistor. In a non-limiting embodiment, a scanning single electron transistor includes a fin formed over a substrate. A source gate is formed over a first portion of the substrate that extends over a sidewall of the fin. A drain gate is formed over a second portion of the substrate that extends over the sidewall of the fin. A plunger gate is formed over a third portion of the substrate that extends over the sidewall of the fin. The plunger gate is positioned between the source gate and the drain gate. The plunger gate is etched back from a topmost surface of the fin such that a quantum dot formed in the fin is not screened by metallic materials in the plunger gate.

Abstract: Provided are a capacitor, a method of preparing the capacitor, and an electronic device including the capacitor, the capacitor including a lower electrode, an upper electrode spaced apart from the lower electrode, a dielectric between the lower electrode and the upper electrode, a first layer between the lower electrode and the dielectric, and a second layer between the dielectric and the upper electrode, wherein the dielectric comprises TiO2 having a rutile phase and is doped with magnesium, the first layer includes a material having a higher work function than that of a material included in the lower electrode, and the second layer includes a dielectric protective material.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.

Abstract: A semiconductor package including a first semiconductor chip and a second semiconductor chip on a first substrate, a thermal conductive adhesive layer on the first semiconductor chip and the second semiconductor chip and including a resin layer, the resin layer including a first heat dissipation filler, the first heat dissipation filler including a liquid metal, and the semiconductor package further including a heat dissipation member on the thermal conductive adhesive layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a first active region, a second active region, a first testing module, and a second testing module. The second active region is separated by the first active region by a scribe line. The scribe line extends along a first direction. The first testing module abuts the first active region and is disposed within the scribe line. The second testing module abuts the second active region and is disposed within the scribe line. The first testing module and the second testing module are arranged along a second direction substantially orthogonal to the first direction.

Abstract: Microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. A conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. A first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.

Abstract: A package comprising an integrated device and a metallization portion. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness. The package may include a substrate and/or a bridge. The substrate may include an interposer.

Abstract: A method of forming a semiconductor device includes: disposing an isolation oxide layer and a shield polysilicon in trenches formed in a substrate, with the shield polysilicon being partially surrounded by the isolation oxide layer; etching the isolation oxide layer; disposing an inter-poly oxide (IPO) layer on an upper surface of the shield polysilicon with the IPO layer laterally surrounded in the trenches by the isolation oxide layer; etching the IPO layer and the isolation oxide layer; lining at least upper sidewalls of the trenches with a gate oxide layer; disposing a gate polysilicon on an upper surface of the IPO layer and on an upper surface of the isolation oxide layer, with the gate polysilicon laterally surrounded by the gate oxide layer; etching the isolation oxide layer so that a thickness of the isolation oxide layer tapers from the shield polysilicon a top opening of the trench.

Abstract: A method for singulating a semiconductor substrate into individual semiconductor devices, comprising: providing a semiconductor substrate having a front surface and a back surface, wherein the semiconductor substrate comprises device regions that are separated from each other by respective predetermined saw streets; forming an interconnect layer on the front surface; etching the front surface at the predetermined saw streets to form respective frontside openings each having a first depth, wherein the first depth is smaller than a thickness of the semiconductor substrate; attaching a semiconductor element onto the front surface in each device region; and etching the back surface at the respective predetermined saw streets to form respective backside openings each having a second depth, wherein each frontside opening is at least partially aligned with the backside opening at the same saw street to singulate the device regions of the semiconductor substrate into individual semiconductor devices.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a stack of composite conductive structures disposed on the first redistribution structure, and an insulating encapsulation disposed on the first redistribution structure and laterally covering the semiconductor die and the stack of composite conductive structures. The stack of composite conductive structures includes a lower tier and an upper tier stacked upon the lower tier. Each of the lower tier and the upper tier includes a support layer, through material vias (TMVs) penetrating through the support layer, and a conductive adhesive member underlying the support layer and the TMVs.

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.

Abstract: A semiconductor package carrier board structure includes a plurality of carrier board bodies and a plurality of supporting bumps. The carrier board body includes a build-up circuit structure and a plurality of conductive blocks bonded to the build-up circuit structure. Adjacent ones of the carrier board bodies are connected to each other with their corresponding conductive blocks. An area formed by the adjacent conductive blocks defines a cutting path. An opening is formed on a surface of each of the conductive blocks at the cutting path. The supporting bumps are erected between the adjacent openings. As such, each of the supporting bumps corresponds to a position overlapping the cutting path to provide the support function of the semiconductor package carrier board structure when performing the semiconductor packaging operation. After performing the singulation operation, the supporting bumps can be completely removed and one side of the openings can be exposed.

Abstract: Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package may include a lower substrate, a lower semiconductor chip, a redistribution layer, an upper semiconductor chip, and a through electrode. The lower substrate may include a first dielectric layer, a first conductive pattern having a wiring pattern and an under-bump pattern, a second dielectric layer, and a second conductive pattern. The under-bump pattern may include a first head part and a first tail part. The first head part may have a first lateral surface on the first dielectric layer that is inclined to a top surface of the first dielectric layer. The second conductive pattern may have a second lateral surface on the second dielectric layer that is perpendicular to a top surface of the second dielectric layer.

Abstract: A semiconductor module includes a substrate, at least one chip, at least one signal assembly, a first molding compound, and a second molding compound. The chip is disposed on the substrate and electrically connected to the substrate. The signal assembly is disposed on the substrate in a normal direction of the substrate and electrically connected to the substrate. The first molding compound is disposed on the substrate. The first molding compound at least covers the chip and has at least one opening, and the opening exposes the signal assembly. The second molding compound is disposed on the substrate and fills the opening. The second molding compound is located between the signal assembly and the first molding compound, and covers the signal assembly. At least one contact interface is formed between the second molding compound and the first molding compound.

Abstract: A connection structure of vias is provided. The connection structure includes multiple vias which are disposed within an insulting layer to connect electrical signals in upward and downward directions, the multiple vias comprise a first via and a second via disposed in a vertically stacked relationship with each other, the first via and the second via are configured to meet at a same surface, and the second via and the first via are disposed in respectively different numbers.

Abstract: A display device includes a substrate; a light emitting element disposed on the substrate; and a photoconversion layer disposed on the light emitting element and including a photoconversion structure body, of which a viewing angle and color purity are improved by preventing degradation of the quantum dot according to moisture and oxygen in accordance with the photoconversion structure body including a quantum dot and an inorganic protection layer coating a surface of the quantum dot in the photoconversion layer may be provided.

Abstract: A stacked wiring structure includes a first wiring substrate and a second wiring substrate. The first wiring substrate includes a first glass substrate, multiple first conductive through vias penetrating through the first glass substrate, and a first multi-layered redistribution wiring structure disposed on the first glass substrate. The second wiring substrate includes a second glass substrate, multiple second conductive through vias penetrating through the second glass substrate, and a second multi-layered redistribution wiring structure disposed on the second glass substrate. The first conductive through vias are electrically connected to the second conductive through vias. The first glass substrate is spaced apart from the second glass substrate. The first multi-layered redistribution wiring structure is spaced apart from the second multi-layered redistribution wiring structure by the first glass substrate and the second glass substrate.

Abstract: A structure including a conductive region, a dielectric region, and a capping layer is provided. The conductive region is disposed on or embedded in the dielectric region. The capping layer is disposed on the conductive region. A material of the capping layer includes a 2D material.

Abstract: In one example, an electronic device includes an embedded module, which includes a module substrate and module components coupled to the module substrate. A device substrate is coupled to the first module substrate. Device terminals are coupled to the module components and a device encapsulant structure encapsulates the embedded module, the device substrate, and the device terminals. A portion of the device substrate is exposed from the device encapsulant structure and portions of the device terminals are exposed from the device encapsulant structure. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.