Patents Examined by Michael Jung
  • Patent number: 10892363
    Abstract: A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 12, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Noboru Morimoto
  • Patent number: 10886490
    Abstract: Provided is an organic light-emitting device including a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including an emission layer, the organic layer including a low work function metal compound.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Samsung Display Co, , Ltd.
    Inventors: Eungdo Kim, Dongchan Kim, Wonjong Kim, Dongkyu Seo, Dahea Im, Sanghoon Yim, Yoonhyeung Cho, Changwoong Chu
  • Patent number: 10867908
    Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng Ding, So Ra Park, Jeong Hoon Ahn
  • Patent number: 10867918
    Abstract: A power network includes a plurality of power switch units disposed in a first semiconductor layer, arranged in a plurality of columns along a first direction and a plurality of rows along a second direction. The power switch units in even rows are aligned with a center point of a horizontal space between adjacent two of the power switch units in the same row of the odd rows of the power switch units in the first direction. The power switch units in even columns are aligned with a center point of a vertical space between adjacent two of the power switch units in the same column of the odd columns of the power switch units in the second direction. The power network further includes a plurality of second connecting lines disposed in a fourth semiconductor layer and extending in the second direction.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 15, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jerming Lin, Lei Sun, Bing Li
  • Patent number: 10862077
    Abstract: A method of producing a substrate includes an imprint layer forming step of forming an imprint layer on a surface of a foundation layer and boring a contact hole through a location in the imprint layer that overlaps at least a part of a foundation conductive layer of the foundation layer, a groove forming step of, by partially depressing a surface of the imprint layer, forming a conductive layer forming groove at least a part of which communicates with the contact hole, and a conductive layer forming step of forming a conductive layer in the conductive layer forming groove and the contact hole.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 8, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Mikihiro Noma
  • Patent number: 10854726
    Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10854509
    Abstract: A method for making an electrical connection structure includes: providing a substrate; forming a mating layer on the substrate; forming a connecting pad on the mating layer; forming a connecting line on the connecting pad and electrically coupling to the connecting pad; forming a covering layer covering the connecting line; and light irradiating the covering layer. Both the connecting pad and the connecting line are made of a metal or an alloy. The mating layer includes alternating yttrium oxide films and silicon oxide films.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 1, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chin-Yueh Liao, Chia-Lin Liu, Yan-Tang Dai, Hung-Che Lu
  • Patent number: 10854751
    Abstract: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 1, 2020
    Assignee: SONY CORPORATION
    Inventors: Satoru Mayuzumi, Hitoshi Wakabayashi
  • Patent number: 10854676
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 10847602
    Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Huang-Hsien Chang, Tsung-Tang Tsai, Hung-Jung Tu
  • Patent number: 10847471
    Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Jesse C. Jones, Gang Duan, Jason Gamba, Yosuke Kanaoka, Rahul N. Manepalli, Vishal Shajan
  • Patent number: 10833012
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Haojun Zhang, Mahadeva Iyer Natarajan
  • Patent number: 10833200
    Abstract: Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 10833273
    Abstract: A method for manufacturing an organic electronic device according to one embodiment includes: a coating film formation step of applying a coating liquid for a functional layer having a predetermined function onto a plastic substrate to form a coating film; and a heating step of heating and curing the coating film by irradiating the coating film with infrared rays in an infrared heating furnace to form the functional layer. In the heating step, the coating film is heated and cured by the infrared rays while a member of the infrared heating furnace is cooled to 100° C. or less, the member being disposed around the plastic substrate so as to be separate from the plastic substrate.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: November 10, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hidemi Yoshioka
  • Patent number: 10826020
    Abstract: A light-emitting device for use in a display device has enhanced directional light emission, and enhanced on-axis light emission in particular. A light-emitting device includes a layer structure that includes from a non-emitting side: a first electrode layer; a first charge transport layer; an emissive layer; a second charge transport layer; a second electrode layer; an optically transparent layer; and a partially transmitting reflector layer. The light-emitting device comprises a plurality of regions and each region emits light of a different wavelength, such as for example red, green, and blue light-emitting regions. The optically transparent layer is present in at least one of the plurality of regions. The optically transparent layer may be present in more than one of the plurality of regions, and a thickness of the optically transparent layer may differ in different regions to optimize light emission at different wavelengths.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 3, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: James Andrew Robert Palles-Dimmock, Tim Michael Smeeton, David James Montgomery, Nathan James Smith
  • Patent number: 10804271
    Abstract: Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 10797198
    Abstract: Provided is an infrared light emitting device with high emission intensity. The infrared light emitting device includes: a semiconductor substrate; a first compound semiconductor layer; a light emitting layer containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s); a third compound semiconductor layer; and a second compound semiconductor layer containing at least In, Al, and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), in which the first compound semiconductor layer includes, in the stated order, a first A layer, a first B layer, and a first C layer, each containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), and the proportion(s) of the Al composition or the Al composition and the Ga composition of each layer satisfy a predetermined relation(s).
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 6, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Yoshiki Sakurai, Osamu Morohara, Hiromi Fujita
  • Patent number: 10777638
    Abstract: Roughly described, an integrated circuit device includes a semiconductor having an overall length. In successively adjacent longitudinal sequence, the semiconductor includes first, second and third lengths all having a same first conductivity type. One end of the longitudinal sequence (the end adjacent to the first length) can be referred to a source end of the sequence, and the other end (adjacent to the third length) can be referred to as a drain end. Overlying the second length is a first gate conductor, which defines a first body region. Overlying a cascode portion of the third length is a second gate conductor, which defines a second body region. The second gate conductor preferably is longitudinally continuous with the first gate conductor, but if not, then the two are connected together by other conductors. The first body region is recessed relative to the first and third lengths of the semiconductor.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
  • Patent number: 10770354
    Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10770502
    Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiu-Jung Chen, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Volume Chien, Yung-Lung Hsu, Yun-Wei Cheng