Abstract: Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.

Abstract: Disclosed are a display substrate, a preparation method thereof, and a display apparatus. The display substrate includes a display region and a non-display region surrounding the display region, wherein the non-display region includes a first border region at least partially surrounding the display region, a second border region and a lead convergence region located on a side of the display region, the lead convergence region is located between the first border region and the second border region, and the lead convergence region includes two corner regions and an intermediate convergence region located between the two corner regions; a plurality of data line leads, at least located in the first border region and the lead convergence region, and electrically connected with a plurality of data lines in the display region.

Abstract: An embodiment package substrate may include a core portion including a first material having a first bulk modulus and a first coefficient of thermal expansion, and a reinforcing portion including a second material having a second bulk modulus and a second coefficient of thermal expansion. The second bulk modulus may be chosen to be greater than the first bulk modulus and the second coefficient of thermal expansion may be chosen to be less than the first coefficient of thermal expansion. The core portion may include a fiber-reinforced polymer material and the reinforcing portion may include silicon, silicon nitride, or a ceramic material. The second bulk modulus may be greater than or equal to 100 GPa and the second coefficient of thermal expansion may be less than 10 ppm/° C. The reinforcing portion may include four components each respectively located proximate to a respective corner of the package substrate.

Abstract: A semiconductor device may include a substrate having a first surface and a second surface opposite to the first surface, a protection layer on the first surface of the substrate, metal layers in the substrate, extending in a first direction parallel to the first surface, and spaced apart from each other in a second direction perpendicular to the first surface, a via structure vertically penetrating the metal layers and the substrate, a circuit layer on the second surface of the substrate, and a connection terminal on a bottom surface of the circuit layer. Each of the metal layers may have a tetragonal or circular shape, when viewed in a plan view.

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Abstract: A display panel includes an opening area, a display area surrounding at least a part of the opening area, an intermediate area between the opening area and the display area, a light-emitting diode disposed on a substrate in the display area and including a first electrode, a second electrode, and a functional layer between the first electrode and the second electrode a first dam disposed in the intermediate area, a first crack dam located between the first dam and the opening area, and a second crack dam located between the first crack dam and the opening area, wherein the functional layer extends from the display area to the intermediate area, and the functional layer includes a first opening located between the first dam and the first crack dam.

Abstract: A semiconductor package includes a package substrate having a first side and an opposite second side, a semiconductor chip on the first side of the package substrate, a capacitor on the second side of the package substrate, a plurality of connecting terminals on the second side of the package substrate, and a metal line within a trench in the package substrate. The trench extends in a first direction, and the metal line is between the capacitor and the plurality of connecting terminals. The metal line is spaced apart from the capacitor in a second direction that is transverse to the first direction, and a distance between the metal line and the capacitor is 100 ?m or more and 1000 ?m or less.

Abstract: A method of processing a wafer includes a composite substrate forming step of joining a face side of a wafer and a surface of a support substrate to each other with a joint member interposed therebetween, a grinding step of grinding a reverse side of the wafer of the composite substrate to thin down the wafer to a finished thickness, a transfer member affixing step of affixing a transfer member to the reverse side of the wafer, a joint member breaking step of breaking the joint member by applying a laser beam having a wavelength transmittable through the support substrate and absorbable by the joint member to the composite substrate from another surface side of the support substrate, and a transferring step of peeling off the support substrate from the wafer and transferring the wafer to the transfer member.

Abstract: A semiconductor assembly includes a semiconductor device and a POL-RDL package coupled to said device. The device includes an upper surface, a gate pad and at least one source pad disposed on said upper surface. The POL-RDL package includes a dielectric layer having at least one source pad electrically coupled to said at least one source pad of said device and at least one contact pad disposed. At least one trace connection having a resistivity value electrically couples said at least one source pad of said POL-RDL package to said at least one contact pad.

Abstract: A semiconductor package includes a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer having protrusions protruding from the first surface and a plurality of first bonding pads provided on the protrusions, a first semiconductor device mounted on the first redistribution wiring layer via conductive bumps, a plurality of conductive structures respectively extending from the first bonding pads around the first semiconductor device, and a second redistribution wiring layer disposed on the conductive structures and electrically connected to the first redistribution wiring layer.

Abstract: Disclosed are capacitor wires and electronic devices including the same. The capacitor wire comprises a core electrode line having a wire shape extending in a length direction, an outer electrode line that covers at least a portion of the core electrode line and extends in the length direction of the core electrode line, and a dielectric line between the core electrode line and the outer electrode line and extending in the length direction of the core electrode line. The dielectric line has a porous structure including a plurality of holes.

Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package, a first adhesive and a second adhesive. The substrate has a first board surface and a second board surface, and a second region surrounds a first region on the first board surface. The semiconductor package has an upper surface, a lower surface, and a side surface, and is disposed on the first board surface. The first adhesive is formed on the first board surface, in the second region and in a portion of the first region adjacent to the second region. The second adhesive is formed between the side surface and the first adhesive and contacts the side surface and the first adhesive, and the first adhesive and the second adhesive together form a pier adhesive.

Abstract: A semiconductor device including a substrate, lower electrodes disposed on the substrate, at least one support layer in contact with the lower electrodes, a dielectric layer disposed on the lower electrodes, an upper electrode disposed on the dielectric layer, a first interfacial film between the lower electrodes and the dielectric layer, and a second interfacial film between the upper electrode and the dielectric layer. At least one of the first and second interfacial films includes a plurality of layers, wherein the plurality of layers include a first metal element, and a second metal element, and at least one of oxygen \and nitrogen. The lower electrodes include the first metal element. A first region of the first interfacial film includes the second metal element at a first concentration and a second region of the first interfacial film includes the second metal element at a second concentration different from the first concentration.

Abstract: A microelectronic device includes a stack structure including blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The blocks including a stadium structure including opposing staircase structures each having steps comprising edges of the tiers. The blocks further include a filled trench vertically overlying and within horizontal boundaries of the stadium structure. The filled trench includes dielectric liner structures and additional dielectric liner structures having a different material composition than that of the dielectric liner structures and alternating with the dielectric liner structures. The filled trench also includes dielectric fill material overlying an alternating sequence of the dielectric liner structures and additional dielectric liner structures.

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

Abstract: A semiconductor device includes a semiconductor chip including a semiconductor integrated circuit, and a cooling channel formed in the semiconductor chip and providing a moving path for a coolant. An ultrasonic vibrator may be arranged in the cooling channel. The ultrasonic vibrator may vibrate the coolant. By doing so, the stagnation of vapors and/or generation of a vapor film may be reduced or prevented.

Abstract: Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.

Abstract: Disclosed are techniques for integrated circuits (ICs). In an aspect, an IC package includes a package substrate having an upper surface, a lower surface, a first side, and a second side perpendicular to the first side. The package substrate includes a metallization structure. The IC package further includes an IC die attached to the upper surface of the package substrate; first package bumps on the lower surface of the package substrate; and second package bumps on the lower surface of the package substrate. The first package bumps are arranged adjacent to one another along a diagonal direction that is diagonal to the package substrate, and the second package bumps are arranged adjacent to one another along the diagonal direction.

Abstract: Provided are an image display device and an electronic device capable of suppressing burn-in. An image display device includes a plurality of pixels arranged two-dimensionally. The plurality of pixels includes: a first pixel region including a pixel configured to emit light and transmit visible light; a second pixel region arranged around the first pixel region, and including a pixel configured to emit light with an area larger than a light-emitting area of a pixel in the first pixel region; and a third pixel region arranged around the second pixel region, and including a pixel configured to emit light with an area larger than a light-emitting area of a pixel in the second pixel region.

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer; a semiconductor chip on a first surface of the first redistribution structure and including a connection pad electrically connected to the first redistribution layer; an encapsulant that surrounds at least a portion of the semiconductor chip; a second redistribution structure on the encapsulant and including a second redistribution layer; a through-via structure that extends through the encapsulant and electrically connects the first redistribution layer to the second redistribution layer; an organic material layer between the through-via structure and the encapsulant and having an elongation rate greater than an elongation rate of the encapsulant; and a bump structure on a second surface of the first redistribution structure.