Abstract: The embodiments herein are directed to technologies for crosstalk cancellation structures. One semiconductor package includes conductive metal layers separated by insulating layers, the conductive metal layers for routing signals between external package terminals and pads on an integrated circuit device. Signal lines formed in the conductive metal layers have electrode structure (capacitor electrode-like structures) formed for at least adjacent signaling lines of the package terminals. Two of the electrode structures from the adjacent signaling lines are formed opposite each other on different metal layers.

Abstract: The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.

Abstract: Provided is a solid-state imaging element including a support 1 having a photoelectric conversion unit 10 and an optical filter 20 provided on a light incident side with respect to the photoelectric conversion unit 10. The optical filter 20 has two or more kinds of pixels 21, 22, and 23 arranged in a patterned manner and a partition wall 25 disposed between the pixels. A refractive index of the partition wall with respect to light having a wavelength of 533 nm is 1.10 to 1.30, a width W1 of the partition wall is 80 to 150 nm, a refractive index of the pixels with respect to light having a wavelength of 1000 nm is 1.60 to 1.90, a difference between a thickness H1 of the partition wall and a thickness H2 of pixels adjacent to the partition wall is 200 nm or less, and a difference between the refractive index of the partition wall with respect to light having a wavelength of 533 nm and a refractive index of the pixels adjacent to the partition wall with respect to light having a wavelength of 1000 nm is 0.

Abstract: A display substrate, a display panel and a method of manufacturing a display substrate are provided. The display substrate includes: a substrate; a plurality of pixel units including at least a first pixel unit including a first light-emitting region and a first non-light-emitting region; a first light-emitting element arranged in the first light-emitting region, including a first electrode, a light-emitting layer and a second electrode; a scan driving circuit arranged in the first non-light-emitting region; and a first auxiliary electrode located in a first partial region in the first non-light-emitting region, wherein the scan driving circuit includes a plurality of scan driving sub-circuits located in a second partial region in the first non-light-emitting region; an orthographic projection of the first partial region on the substrate overlaps an orthographic projection of the second partial region on the substrate, and the first auxiliary electrode is electrically connected to the second electrode.

Abstract: A light-emitting diode (LED) packaging module includes light-emitting units arranged in an array having m row(s) and n column(s), an encapsulating layer, and a wiring assembly, where m and n each independently represents a positive integer. Each of the light-emitting units includes LED chips each including a chip first surface, a chip second surface, a chip side surface, and an electrode assembly disposed on the chip second surface. The encapsulating layer covers the chip side surface and fills a space among the LED chips. The wiring assembly is disposed on the chip second surface and is electrically connected to the electrode assembly.

Abstract: A microcavity pixel design and fabrication method for an organic light emitting diode (OLED) array with a high aperture ratio suitable for a light field display. This is achieved by laterally overlapping intermediate electrodes and optical filler layers, reducing the lateral spacing. The OLED layers in the design have a uniform white OLED stack, allowing each layer to be deposited across the OLED array, simplifying fabrication. The optical path length for each subpixel's optical microcavity is optimized through the thickness of the optical filler layers, allowing the white OLED stack to be uniform, reducing fabrication complexities.

Abstract: A display substrate includes a base substrate, a thin film transistor array layer, a planarization layer, a first electrode and a pixel definition layer, the pixel definition layer defining a plurality of pixel openings, each pixel opening includes a first edge and a second edge adjacent to each other, the pixel definition layer includes a first pixel definition layer parallel to the first edge and a second pixel definition layer parallel to the second edge. A surface of the first pixel definition layer away from the base substrate is located at a level lower than a surface of the second pixel definition layer away from the base substrate, a groove parallel to the first edge is arranged in a surface of the planarization layer away from the base substrate, at least a part of the first pixel definition layer is arranged in the groove.

Abstract: Disclosed is a display panel, including: a base substrate including a first display region, a second display region, and a routing region: a first anode layer, a first light-emitting layer and a first cathode layer disposed in the first display region and sequentially stacked in a direction going away from the base substrate; a second cathode layer, a second anode layer, a second light-emitting layer, and a third cathode layer disposed in the second display area and sequentially stacked in the direction going away from the base substrate, and a first signal transmission layer disposed in the routing region; wherein the first signal transmission layer is connected to the second cathode layer and the first cathode layer, and the first signal transmission layer is further configured to receive a power supply signal.

Abstract: Embodiments of the present application provide a display device and a display terminal. A protective layer is disposed outside the display panel, and a plurality of heat dissipation capsules are dispersedly disposed in the protective layer. The heat dissipation capsules are provided with a phase change material. The phase change material can change the material state thereof and absorb a large amount of heat, thereby cooling the display device and the display terminal, solving the problem of difficult heat dissipation of the display device and the display terminal, and improving the image display quality.

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Abstract: A light emitting device includes: a base substrate; a plurality of unit regions provided on the base substrate; a barrier disposed at a boundary of the unit regions to surround each of the unit regions; a dam disposed in each of the unit regions to be spaced apart from the barrier; a first electrode provided in each of unit light emitting regions surrounded by the dam; a second electrode disposed in each of the unit light emitting regions, the second electrode of which at least one region is provided opposite to the first electrode; and one or more LEDs provided in each of the unit light emitting regions, the one or more LEDs being electrically connected between the first electrode and the second electrode.

Abstract: Disclosed is a strip substrate including a dielectric layer that has a plurality of unit regions spaced apart from each other in a first direction and a saw line region between the unit regions, a plurality of conductive dummy patterns on corresponding unit regions of the dielectric layer, a plurality of saw line patterns on the saw line region of the dielectric layer and extending in a second direction that intersects the first direction, and a protection pattern that covers the dielectric layer. Ends of the conductive dummy patterns are spaced apart from each other in a direction parallel to the first direction. Ends of the saw line patterns are spaced apart from each other in a direction parallel to the second direction. The protection pattern is between the ends of the conductive dummy patterns and between the ends of the saw line patterns.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: A semiconductor device includes a substrate including a cell region and a scribe lane surrounding the cell region, a first overlay pattern structure, which is on the scribe lane and includes first sub-patterns extending in a first direction parallel to an upper surface of the substrate, second sub-patterns extending in a second direction parallel to the upper surface of the substrate, a first outer fence surrounding the first sub-patterns and the second sub-patterns in a plan view and defining a first overlay pattern region, and a first inner fence in the first overlay pattern region and between the first sub-patterns and the second sub-patterns, and a lower structure in the cell region and on the scribe lane and between the first sub-patterns, the second sub-patterns, the first outer fence, and the first inner fence.

Abstract: A display device may include a plurality of pixel circuits disposed adjacent to each other, the plurality of pixel circuits including a plurality of active patterns disposed to correspond to the pixel circuits, respectively. Each of the active patterns includes a first initialization channel region to which an initialization voltage is applied, a second initialization channel region to which the initialization voltage is applied, and a third initialization channel region to which the initialization voltage is applied, the second initialization channel region of each of the active patterns is connected to the first initialization channel region of the adjacent active patterns, and a first end region of the third initialization channel region is connected between the first initialization channel region and the second initialization channel region.

Abstract: Provided is a compound capable of improving luminous efficiency, stability and lifetime of an organic electronic device, an organic electric element using the same, and an electronic device comprising the element.

Abstract: Described is a technique capable of optimizing a timing of a maintenance process.

Abstract: An object is to provide a display device having a function of emitting visible light and infrared light and an imaging function. Another object is to increase the definition without changing the density of imaging elements while the high resolution of an image displayed on a display device is kept. The display device has a layout in which a light-receiving region of an imaging element is provided between light-emitting regions of a plurality of light-emitting elements over one substrate. In the imaging function of the display device, as a means for increasing the definition of a captured image, the definition is increased without changing the density of imaging elements by capturing an image by time division.

Abstract: The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. More particularly, the present disclosure relates to a method of forming a sensor device and a bond pad in the same dielectric region. The present disclosure also relates to the semiconductor devices formed by the method disclosed herein.