Abstract: A terminal mounted in advance on a battery of an instrument that is a management target wirelessly transmits a battery state obtained by detecting an electric property related to a remaining battery amount of the battery and a terminal ID for identifying the terminal, and a management device displays remaining amount information related to the battery remaining amount on a screen based on the terminal ID and the battery state received from the terminal. This allows a user to easily figure out the remaining amount of a battery being used in an existing instrument.

Abstract: A protection film for an electronic device includes an adhesive layer including a first surface to which an electronic device is attached, and a film layer which contacts a second surface of the adhesive layer and includes at least one member, where a thickness of the adhesive layer satisfies Inequality 1: z?(5.1x+57.4)·ln(y)?(14.7x+140.5), where z is the thickness of the adhesive layer in terms of micrometers, x is a modulus of a member of the film layer which directly contacts the adhesive layer in terms of gigapascals, and y is a total thickness of the film layer in terms of micrometers.

Abstract: This disclosure relates generally to thermal management fluid systems. This disclosure relates more particularly to dielectric thermal management fluid systems useful in cooling electronic devices such as lithium-ion batteries, and methods of using such thermal management fluids.

Abstract: The present description concerns an optoelectronic device (300) including: a vertical stack of first (101) and second (105) semiconductor layers forming a PN junction, and of a third conductive layer (107) arranged on top of and in contact with the surface of the second layer opposite to the first layer; a peripheral trench (110) crossing the third (107) and second (105) layers, said trench laterally delimiting a portion of the third layer (107) and a portion of the second layer (105); in said trench (110), a conductive spacer (301) in contact with a lateral side of said portion of the third layer (107); and in said trench (110), an insulated conductive gate (113, 111) extending against a lateral side of the conductive spacer (301) and against a lateral side of said portion of the second layer.

Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Abstract: A display device includes a light-emitting element layer including a plurality of light-emitting elements. The light-emitting element layer includes, for each of the plurality of light-emitting elements, a first electrode and a plurality of openings exposing the first electrode, and includes an edge cover covering an end portion of the first electrode, a plurality of light-emitting layers covering each of the plurality of openings, and a second electrode that is common to the plurality of light-emitting elements and covers the plurality of light-emitting layers. The second electrode includes a metal nanowire. Furthermore, the light-emitting element layer includes an auxiliary wiring line provided in a lattice pattern in a position overlapping the edge cover, and the auxiliary wiring line and the metal nanowire are electrically connected to each other.

Abstract: An electronic device includes a substrate, an upper conductive layer, and a lower conductive layer. The substrate has a plurality of inner vias and has an upper surface and a lower surface. The upper conductive layer includes an upper ground trace and an upper signal pad disposed on the upper surface. The upper ground trace is electrically connected to the ground vias and has an upper hollow portion exposing a part of the upper surface. The upper signal pad is disposed on the part of the upper surface exposed by the upper hollow portion and electrically connected to the signal via. The lower conductive layer includes a lower ground trace and a lower signal pad disposed on the lower surface. The lower conductive trace is electrically connected to the ground vias and has a lower hollow portion exposing a part of the lower surface. The lower signal pad is disposed on the part of the lower surface exposed by the lower hollow portion and electrically connected to the signal via.

Abstract: An equipment for inspecting a secondary battery is provided. The equipment includes a loading device on which a secondary battery is loaded in an upright position, and a side portion inspecting device which inspects a side portion of the secondary battery loaded on the loading device, wherein the side portion inspecting device comprises an elevation unit which lifts the secondary battery loaded on the loading device so as to be withdrawn out of the loading device and allows the secondary battery to return to its original position after a first period of time elapses and a side portion inspecting unit which captures an image of the side portion of the secondary battery, which is withdrawn out of the loading device by the elevation unit, thereby inspecting the side portion of the secondary battery.

Abstract: A light-emitting element having high emission efficiency is provided. The light-emitting element includes a first organic compound, a second organic compound, and a third organic compound. The first organic compound has a function of converting triplet excitation energy into light emission. The second organic compound is preferably a TADF material. The third organic compound is a fluorescent compound. Light emitted from the light-emitting element is obtained from the third organic compound. Triplet excitation energy in a light-emitting layer is transferred to the third organic compound by reverse intersystem crossing caused by the second organic compound or through the first organic compound.

Abstract: A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.

Abstract: A wiring substrate includes a resin insulating layer, a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer, a conductor pad formed on the resin insulating layer and connected to the via conductor, a coating insulating layer formed on the resin insulating layer such that the coating insulating layer is covering the conductor pad, and a metal post formed on the conductor pad and protruding from the coating insulating layer. The conductor pad is formed such that a central axis of the conductor pad is shifted in a predetermined direction with respect to a central axis of the via conductor, and the metal post is formed such that a central axis of the metal post is shifted in the predetermined direction with respect to the central axis of the conductor pad.

Abstract: A microcavity pixel design and fabrication method for an organic light emitting diode (OLED) array with a high aperture ratio suitable for a light field display. This is achieved by laterally overlapping intermediate electrodes and optical filler layers, reducing the lateral spacing. The OLED layers in the design have a uniform white OLED stack, allowing each layer to be deposited across the OLED array, simplifying fabrication. The optical path length for each subpixel's optical microcavity is optimized through the thickness of the optical filler layers, allowing the white OLED stack to be uniform, reducing fabrication complexities.

Abstract: A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Abstract: Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

Abstract: In a semiconductor device having a main cell region and a sense cell region, a main contact trench and a sense contact trench extend in one direction. When viewed from a stacking direction of a drift layer and a body layer, in the one direction, the main contact trench and a first impurity region disposed in the main cell region protrude more than a main upper electrode toward a sense upper electrode, and the sense contact trench and the first impurity region disposed in the sense cell region protrude more than the sense upper electrode toward the main upper electrode.

Abstract: To provide a wiring substrate, an electronic device, and an electronic module the size of which can be easily reduced and the strength of which can be maintained. A wiring substrate includes an insulation substrate and an electrical wiring structure. The insulation substrate includes a recess section in one surface. A frame portion of the insulation substrate that forms a side surface which connects an opened surface and a bottom surface of the recess section to each other includes a first conductive portion having a plate shape in the frame portion.

Abstract: To provide a semiconductor device further reduced in size. A semiconductor device including: a multilayer wiring board one surface of which is provided with an external connection terminal; and a plurality of active components that are provided to be stacked inside the multilayer wiring board and are connected to the external connection terminal via a connection via. The plurality of active components include a first active component provided on another surface side that is opposite to the one surface, and a second active component that is provided closer to the one surface than the first active component is and has a smaller planar area than the first active component.

Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.

Abstract: A positive electrode for a secondary battery includes a positive electrode active material layer, which includes a positive electrode active material including a lithium transition metal oxide which contains nickel, cobalt, and manganese and has an atomic ratio of nickel in total transition metals of 80 atm % or more, and a metal oxide including a metallic element having a binding potential with lithium of 0.5 V to 4 V. A secondary battery including the positive electrode is also provided.