Abstract: A foldable electronic device module includes: a glass-containing cover element having a thickness from about (25) ?m to about (200) ?m, an elastic modulus from about (20) to (140) GPa, and first and second primary surfaces; a stack comprising: (a) an interlayer having an elastic modulus from about (0.01) to (10) GPa and a thickness from about 50 to (200) ?m, and (b) a flexible substrate having a thickness from about (100) to (200) ?m; and a first adhesive joining the stack to the cover element, and comprising an elastic modulus from about (0.001) to (10) GPa and a thickness from about (5) to (25) ?m. Further, the module comprises an impact resistance characterized by tensile stresses of less than about (4100) MPa and less than about (8300) MPa at the first and second primary surfaces of the cover element, respectively, upon an impact in a Pen Drop Test.

Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

Abstract: An animal wellness notification system includes an attachment body configured to securely engage with an ear of the animal; an elongated temperature probe secured to the attachment body and configured to extend within the ear of the animal; a housing secured to the attachment body; a computer disposed within the housing and operably associated with the temperature probe; and a notification device in data communication with the computer, the notification device being configured to provide notice if a temperature of the animal goes beyond a determined threshold.

Abstract: To make it easy to address the case in which a chromatograph does not appropriately operate. A chromatograph (liquid chromatograph 100) for analyzing a sample by supplying an eluent and the sample and separating a component contained in the sample to detect the component, the chromatograph including: a detection portion (controller 170) configured to detect a fault in the analysis; and an operation controller (controller 170) configured to cause a constituent element related to the analysis to perform at least one of an operation for identifying a factor of the fault and an operation for avoiding the fault.

Abstract: A compound comprising a first ligand LA of Formula I or Formula II: wherein A1 and A2 are each independently C or Si; wherein each RA, and RB independently represents mono to the maximum allowable substitution, or no substitution; wherein each X1, X2, and X3 is independently C or N; wherein each R, R1, R2, R3, R4 and RA is independently a hydrogen or a substituent selected from the group consisting of deuterium, halogen, alkyl, cycloalkyl, heteroalkyl, heterocycloalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, boryl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carboxylic acid, ether, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; wherein LA is complexed to a metal M; wherein M is optionally coordinated to one or more other ligands; wherein the ligand LA is optionally linked with the one or more other ligands to form a tridentate, tetradentate, pentadentate, or hexadentate ligand; and wherein any two substituents are optionally j

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

Abstract: By using a polycyclic aromatic compound as a material for a light-emitting layer, formed by connecting a plurality of aromatic rings with a boron atom and an oxygen, sulfur, or selenium atom, which have been substituted by a specific aryl such as anthracene, an organic EL element having at least one of excellent quantum efficiency and element life can be provided.

Abstract: A training set for use during content generation is generated by applying a first machine learning process P1 to a first finite sequence s wherein s has a length Ls, to generate a first statistical model M(s). The first statistical model M(s) is sampled using a first sampling process G to generate a second finite sequence t wherein t has a length Lt. A second machine learning process P2 is applied to the second finite sequence t to generate a second statistical model M(t), wherein no substring of the second finite sequence t of length d is identical to a substring of the first finite sequence s, wherein d is a predetermined number of elements in a sequence.

Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.

Abstract: An organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer. The emission layer includes at least one organometallic compound of Formula 1, and at least one selected from a second compound and a third compound, where the organometallic compound, the second compound, and the third compound are different from each other.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.

Abstract: A display device and a method for manufacturing a display device are provided. The display device includes an array substrate and a cover plate. The array substrate is a silicon-based organic light-emitting diode array substrate. An orthographic projection of the array substrate in a plane parallel to the array substrate covers an orthographic projection of the cover plate in the plane, the orthographic projection of the array substrate includes a plurality of edges, the orthographic projection of the cover plate includes a plurality of edges, the plurality of edges of the array substrate are in one-to-one correspondence to the plurality of edges of the cover plate. At least two edges of the orthographic projection of the array substrate do not overlap with corresponding edges of the orthographic projection of the cover plate and are located outside the orthographic projection of the cover plate.

Abstract: A stretchable display panel having a plurality of encapsulated islands and a plurality of bridges connecting the plurality of encapsulated islands is provided. The stretchable display panel includes a stretchable base substrate; a flexible base wall on the stretchable base substrate, the flexible base wall substantially enclosing a substantially enclosed space; an adhesive layer on the stretchable base substrate and substantially enclosed in the substantially enclosed space; and a plurality of light emitting elements on a side of the adhesive layer away from the stretchable base substrate. A respective one of the plurality of encapsulated islands includes at least one of the plurality of light emitting elements encapsulated therein on the stretchable base substrate.

Abstract: The present disclosure provides an organic light emitting diode comprising a first electrode; a second electrode facing the first electrode; and an emitting material layer. The emitting material layer includes a p-type host, a n-type host and a phosphorescent dopant and positioned between the first electrode and the second electrode, wherein a first energy level of a HOMO of the p-type host is equal to or lower than a second energy level of a HOMO of the n-type host, and a difference between an energy level of a singlet state of the n-type host and an energy level of a triplet state of the n-type host is greater than 0.3 eV and smaller than 0.5 eV.

Abstract: A die attach system is provided. The die attach system includes: a support structure for supporting a substrate; a die supply source including a plurality of die for attaching to the substrate; and a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool having a contact portion for contacting the die during a transfer from the die supply source to the substrate, the bond head including a spring portion engaged with the bond tool such that the spring portion is configured to compress during pressing of the die against the substrate using the contact portion of the bond tool.

Abstract: Embodiments of the present application provide an integrated circuit and a layout method thereof. First, a first pitch of a first standard cell having a maximum gate length in multiple standard cells in an integrated circuit is determined. The first pitch is a distance between a central axis of a polysilicon gate in the first standard cell and central axes of virtual polysilicon gates in the first standard cell. Then, a distance between a polysilicon gate and virtual polysilicon gates in each of the standard cells is adjusted by using the first pitch and a gate length of each of the standard cells. After the adjustment, a distance between a central axis of the polysilicon gate in each of the standard cells and central axes of the virtual polysilicon gates in each of the standard cells is the same as the first pitch.

Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.