Abstract: A three-dimensional AND flash memory device includes a stack structure, a channel pillar, a first conductive pillar and a second conductive pillar, and a charge storage structure. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar extends through the stack structure. The first conductive pillar and the second conductive pillar are located in and electrically connected with the channel pillar. The first conductive pillar includes a first metal silicide pillar, and the second conductive pillar includes a second metal silicide pillar. The charge storage structure is located between the gate layers and the channel pillar.

Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Abstract: A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.

Abstract: The display device includes a substrate including a first resin layer, a second resin layer overlapping the first resin layer, and a first inorganic insulating layer between the first resin layer and the second resin layer, and having flexibility, a display region provided on the substrate, a terminal region arranged outside the display region on the substrate, and a bending region arranged between the display region and the terminal region. A thickness of the second resin layer is larger than a thickness of the first resin layer. The substrate includes a first region and a second region. The first resin layer, the first inorganic insulating layer, and the second resin layer are laminated in the first region. The first resin layer and the second resin layer are laminated in the second region and the first inorganic insulating layer is not laminated in the second region.

Abstract: Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

Abstract: A display device may include a substrate including a display area and a transmission area located on an outer side of the display area, a display unit in the display area on the substrate, a thin-film encapsulation layer that covers the display unit, and a first dam between the thin-film encapsulation layer and the transmission area on the substrate, and an end portion of the thin-film encapsulation layer may be located on an inner side of the first dam.

Abstract: A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, and a metal film 70 disposed in a part of the interposer 20 that is in contact with a sample stage 30 having a cooling function, and a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22.

Abstract: This disclosure provides an array substrate, a fabrication method thereof, and a display device. The array substrate includes a P-type driving transistor, an N-type first transistor, a capacitor, a base substrate, a first conductive layer laminated at a side of the base substrate, a first dielectric layer laminated at a side of the first conductive layer away from the base substrate, a first buffer layer laminated at a side of the first dielectric layer facing away from the base substrate and having a slot, and a second conductive layer laminated at a side of the first buffer layer facing away from the base substrate. The second conductive layer includes a second conductive portion configured as the gate electrode of the first transistor, and a third conductive portion located at the bottom of the slot to form the second electrode of the capacitor.

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer.

Abstract: A display device including a display panel having a foldable area, a support member disposed on a bottom surface of the display panel and including a plurality of openings formed in the foldable area, and an elastic member disposed on a bottom surface of the support member and overlapping the openings in the foldable area.

Abstract: A composite solid electrolyte (410) for lithium batteries can include a solid polymer (440), a lithium salt (450) distributed in the solid polymer (440), and lithium iron phosphate (460) distributed in the solid polymer (440). A solid state lithium battery cell (400) can include a composite solid electrolyte layer (410), an anode (420) containing lithium in contact with a first surface of the composite solid electrolyte layer (410): and a cathode (430) in contact with a second surface of the composite solid electrolyte layer (410). The composite solid electrolyte layer (410) can include a solid polymer (440), a lithium salt (450) distributed in the solid polymer (440), and lithium iron phosphate (460) distributed in the solid polymer (440).

Abstract: A display module includes a display panel including a plurality of pixels, a carrier panel on a rear surface of the display panel, and an adhesive layer disposed between the display panel and the carrier panel, where the adhesive layer is in contact with the carrier panel. Lateral surfaces of the adhesive layer are recessed from lateral surfaces of the carrier panel.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: An inductor structure is provided. A plurality of first and second conductive posts have end surfaces corresponding in profile to ends of first conductive sheets, respectively. As such, the profiles of the end surfaces of the first and second conductive posts are non-cylindrical so as to increase the contact area between the first conductive sheets and the first and second conductive posts, thereby improving the conductive quality and performance of the inductor. Further, since the first and second conductive posts are formed by stacking a plurality of post bodies on one another, the number and cross-sectional area of loops are increased so as to increase the inductance value. A method for fabricating the inductor structure, an electronic package and a fabrication method thereof, and a method for fabricating a packaging carrier are further provided.

Abstract: The present application discloses a display panel and an electronic device. The display panel includes a display area and a redundant pixel area located on at least one side of the display area. The display panel includes a substrate, a power supply wire, a light-emitting function layer, and a cathode disposed in sequence. At least a part of the power supply wire is located in the redundant pixel area; the light-emitting function layer covers the display area and the redundant pixel area; and the cathode is electrically connected to the power supply wire.

Abstract: An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value.

Abstract: The present invention relates to methods for fabricating vertical homogenous and heterogeneous two-dimensional structures, the fabricated vertical two-dimensional structures, and methods of using the same. The methods demonstrated herein produce structures that are free standing and electrically isolated.

Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.

Abstract: The present disclosure provides an electronic device including a substrate, a first pad, an insulating layer, a second pad, a conductive element and a chip. The first pad is disposed on the substrate. The insulating layer is disposed on the first pad and has a plurality of first openings. The second pad is electrically connected to the first pad through the first openings. The conductive particle is disposed on the second pad. The chip is electrically connected to the second pad through the conductive element. In a top view of the electronic device, the first openings are arranged along a long edge of the first pad, and an outline of at least one first opening has a curved shape.