Patents Examined by Michael Jung
  • Patent number: 12089445
    Abstract: This disclosure provides an array substrate, a fabrication method thereof, and a display device. The array substrate includes a P-type driving transistor, an N-type first transistor, a capacitor, a base substrate, a first conductive layer laminated at a side of the base substrate, a first dielectric layer laminated at a side of the first conductive layer away from the base substrate, a first buffer layer laminated at a side of the first dielectric layer facing away from the base substrate and having a slot, and a second conductive layer laminated at a side of the first buffer layer facing away from the base substrate. The second conductive layer includes a second conductive portion configured as the gate electrode of the first transistor, and a third conductive portion located at the bottom of the slot to form the second electrode of the capacitor.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 10, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yipeng Chen, Ling Shi, Wenqiang Li
  • Patent number: 12087681
    Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: September 10, 2024
    Assignee: Rambus Inc.
    Inventors: Shahram Nikoukary, Jonghyun Cho, Nitin Juneja, Ming Li
  • Patent number: 12082408
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: September 3, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., ˜LTD.
    Inventors: Yuancheng Yang, Wenxi Zhou, Zhiliang Xia, Wei Liu
  • Patent number: 12075689
    Abstract: A display device including a display panel having a foldable area, a support member disposed on a bottom surface of the display panel and including a plurality of openings formed in the foldable area, and an elastic member disposed on a bottom surface of the support member and overlapping the openings in the foldable area.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 27, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dongwoo Seo, Dong Jin Park, Jai Ku Shin, Sung-Chul Choi
  • Patent number: 12074284
    Abstract: A composite solid electrolyte (410) for lithium batteries can include a solid polymer (440), a lithium salt (450) distributed in the solid polymer (440), and lithium iron phosphate (460) distributed in the solid polymer (440). A solid state lithium battery cell (400) can include a composite solid electrolyte layer (410), an anode (420) containing lithium in contact with a first surface of the composite solid electrolyte layer (410): and a cathode (430) in contact with a second surface of the composite solid electrolyte layer (410). The composite solid electrolyte layer (410) can include a solid polymer (440), a lithium salt (450) distributed in the solid polymer (440), and lithium iron phosphate (460) distributed in the solid polymer (440).
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 27, 2024
    Assignee: University of Utah Research Foundation
    Inventors: Jan D. Miller, Xuming Wang, Qinyu Zhu
  • Patent number: 12069935
    Abstract: A display module includes a display panel including a plurality of pixels, a carrier panel on a rear surface of the display panel, and an adhesive layer disposed between the display panel and the carrier panel, where the adhesive layer is in contact with the carrier panel. Lateral surfaces of the adhesive layer are recessed from lateral surfaces of the carrier panel.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: August 20, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Geunwoo Yug
  • Patent number: 12063784
    Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: August 13, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Liang Chen, Chao Sun, Wei Liu, Wenshan Xu, Wu Tian, Ning Jiang, Lei Xue
  • Patent number: 12062685
    Abstract: An inductor structure is provided. A plurality of first and second conductive posts have end surfaces corresponding in profile to ends of first conductive sheets, respectively. As such, the profiles of the end surfaces of the first and second conductive posts are non-cylindrical so as to increase the contact area between the first conductive sheets and the first and second conductive posts, thereby improving the conductive quality and performance of the inductor. Further, since the first and second conductive posts are formed by stacking a plurality of post bodies on one another, the number and cross-sectional area of loops are increased so as to increase the inductance value. A method for fabricating the inductor structure, an electronic package and a fabrication method thereof, and a method for fabricating a packaging carrier are further provided.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: August 13, 2024
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventor: Shih-Ping Hsu
  • Patent number: 12063828
    Abstract: The present application discloses a display panel and an electronic device. The display panel includes a display area and a redundant pixel area located on at least one side of the display area. The display panel includes a substrate, a power supply wire, a light-emitting function layer, and a cathode disposed in sequence. At least a part of the power supply wire is located in the redundant pixel area; the light-emitting function layer covers the display area and the redundant pixel area; and the cathode is electrically connected to the power supply wire.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 13, 2024
    Assignees: Huizhou China Star Optoelectronics Display Co., Ltd., TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Weijing Zeng
  • Patent number: 12057487
    Abstract: An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 12051588
    Abstract: The present invention relates to methods for fabricating vertical homogenous and heterogeneous two-dimensional structures, the fabricated vertical two-dimensional structures, and methods of using the same. The methods demonstrated herein produce structures that are free standing and electrically isolated.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 30, 2024
    Assignee: The Penn State Research Foundation
    Inventors: Joshua Alexander Robinson, Rafael Vila
  • Patent number: 12046548
    Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong
  • Patent number: 12046547
    Abstract: The present disclosure provides an electronic device including a substrate, a first pad, an insulating layer, a second pad, a conductive element and a chip. The first pad is disposed on the substrate. The insulating layer is disposed on the first pad and has a plurality of first openings. The second pad is electrically connected to the first pad through the first openings. The conductive particle is disposed on the second pad. The chip is electrically connected to the second pad through the conductive element. In a top view of the electronic device, the first openings are arranged along a long edge of the first pad, and an outline of at least one first opening has a curved shape.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: July 23, 2024
    Assignee: InnoLux Corporation
    Inventors: Mei-Chi Hsu, Yu-Chin Lin, Yu-Ting Liu
  • Patent number: 12048139
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: July 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sen Li, Jun Xia
  • Patent number: 12048230
    Abstract: To provide a display device that is suitable for increasing in size, a display device in which display unevenness is suppressed, or a display device that can display an image along a curved surface. The display device includes a first display panel and a second display panel each including a pair of substrates. The first display panel and the second display panel each include a first region which can transmit visible light, a second region which can block visible light, and a third region which can perform display. The third region of the first display panel and the first region of the second display panel overlap each other. The third region of the first display panel and the second region of the second display panel do not overlap each other.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Hisao Ikeda
  • Patent number: 12040265
    Abstract: In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: July 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yiqi Tang, Rajen Manicon Murugan, Li Jiang
  • Patent number: 12041840
    Abstract: Embodiments of the present disclosure generally relate to methods for forming an organic light emitting diode (OLED) device. Forming the OLED device comprises depositing a first barrier layer on a substrate having an OLED structure disposed thereon. A first sublayer of a buffer layer is then deposited on the first barrier layer. The first sublayer of the buffer layer is cured with a mixed gas plasma. Curing the first sublayer comprises generating water from the mixed gas plasma in a process chamber in which the curing occurs. The deposition of the first sublayer and the curing of the first sublayer is repeated one or more times to form a completed buffer layer. A second barrier layer is then deposited on the completed buffer layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: July 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Wen-Hao Wu, Jrjyan Jerry Chen
  • Patent number: 12027608
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
  • Patent number: 12027454
    Abstract: A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: July 2, 2024
    Assignee: Absolics Inc.
    Inventors: Youngho Rho, Sungjin Kim, Jincheol Kim
  • Patent number: 12018036
    Abstract: Provided are transition metal compounds having 5-membered carbocyclic or heterocyclic ring in a unique configuration of fused rings per Formula I The compounds show improved phosphorescent emission in red to near IR region and are useful as emitter materials in organic electroluminescence device.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: June 25, 2024
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Chun Lin, Pierre-Luc T. Boudreault, Bert Alleyne, Zhiqiang Ji, Suman Layek