Patents Examined by Michael Lulis
  • Patent number: 8216857
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8216877
    Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: July 10, 2012
    Assignee: Promos Technologies Inc.
    Inventors: Yen Chuo, Hong-Hui Hsu
  • Patent number: 8193030
    Abstract: Nonvolatile memory devices may be fabricated to include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-wook Moon, Joong S. Jeon, El Mostafa Bourim, Hyun-deok Yang
  • Patent number: 8193598
    Abstract: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: June 5, 2012
    Assignee: The Regents of the University of California
    Inventors: Mary M. Eshaghian-Wilner, Alexander Khitun, Kang L. Wang
  • Patent number: 8188454
    Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: May 29, 2012
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 8188535
    Abstract: An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8154004
    Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Mirmajid Seyyedy, Glen Hush
  • Patent number: 8153447
    Abstract: A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to have a column type, where a ferroelectric material is filled in a space where the first electrode are separated from the second electrode. The serial PN diode switch, which is connected between a bit line and the ferroelectric capacitor, selectively switches a current direction between the bit line and the ferroelectric capacitor depending on voltage change between the bit line and the ferroelectric capacitor.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8148708
    Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun-Taek Hwang, Yu-Jin Lee
  • Patent number: 8143611
    Abstract: A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: March 27, 2012
    Assignee: Canon Anelva Corporation
    Inventors: Young-suk Choi, Koji Tsunekawa
  • Patent number: 8138573
    Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ethan H. Cannon, Alvin W. Strong
  • Patent number: 8115232
    Abstract: The present invention provides of a three-dimensional bicontinuous heterostructure, a method of producing same, and the application of this structure towards the realization of photodetecting and photovoltaic devices working in the visible and the near-infrared. The three-dimensional bicontinuous heterostructure includes two interpenetrating layers which are spatially continuous, they are include only protrusions or peninsulas, and no islands. The method of producing the three-dimensional bicontinuous heterostructure relies on forming an essentially planar continuous bottom layer of a first material; forming a layer of this first material on top of the bottom layer which is textured to produce protrusions for subsequent interpenetration with a second material, coating this second material onto this structure; and forming a final coating with the second material that ensures that only the second material is contacted by subsequent layer.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: February 14, 2012
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Sargent, Steve McDonald, Shiguo Zhang, Larissa Levina, Gerasimos Konstantatos, Paul Cyr
  • Patent number: 8097912
    Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: January 17, 2012
    Assignee: Macronix International Co. Ltd.
    Inventors: Cheng-Ming Yih, Chu-Ching Wu, Huei-Huarng Chen
  • Patent number: 8089132
    Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: January 3, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Haiwen Xi, Dimitar V. Dimitrov, Dexin Wang
  • Patent number: 8076195
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Mike Violette
  • Patent number: 8053761
    Abstract: Disclosed are methods of fabricating organic thin film transistors composed of a substrate, a gate electrode, a gate insulating film, metal oxide source/drain electrodes, and an organic semiconductor layer. The methods include applying a sufficient quantity of a self-assembled monolayer compound containing a live ion to the surfaces of the metal oxide electrodes to form a self-assembled monolayer. The presence of the live ion at the interface between the metal oxide electrodes and the organic semiconductor layer modifies the relative work function of these materials. Further, the presence of the self-assembled monolayer on the gate insulating film tends to reduce hysteresis. Accordingly, organic thin film transistors fabricated in accord with the example embodiments tend to exhibit improved charge mobility, improved gate insulating film properties and decreased hysteresis associated with the organic insulator.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Seok Hahn, Bon Won Koo, Joo Young Kim, Kook Min Han, Sang Yoon Lee
  • Patent number: 8039890
    Abstract: A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Six(SiO2)y(Si3N4)1-yMz (M is an element other than Si, O, and N, x?0, 1?y?0, z?0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mari Matsumoto, Ryuji Ohba, Shinobu Fujita
  • Patent number: 8039372
    Abstract: A phase changeable memory device is manufactured by forming at least one insulating layer on a substrate. A preliminary first electrode is formed on the insulating layer. The preliminary first electrode is partially etched to form a first electrode electrically connected to the substrate. After the preliminary first electrode is formed, both sidewalls of the preliminary first electrode are partially etched isotropically to form a first electrode having a uniform width and height. A phase changeable material layer pattern and a second electrode are subsequently formed on the first electrode. Related devices also are described.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Ki Min, Tae-Eun Kim, Byoung-Moon Yoon
  • Patent number: 8035096
    Abstract: A switching device according to the present invention includes ion conductive layer 23 containing titanium oxide, first electrode 21 provided in contact with ion conductive layer 23, and second electrode 22 provided in contact with ion conductive layer 23 and which can supply metal ions to ion conductive layer 23.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: October 11, 2011
    Assignee: NEC Corporation
    Inventor: Noriyuki Iguchi
  • Patent number: 8026503
    Abstract: A phase-change memory cell structure includes a bottom diode on a substrate; a heating stem on the bottom diode; a first dielectric layer surrounding the heating stem, wherein the first dielectric layer forms a recess around the heating stem; a phase-change storage cap capping the heating stem and the first dielectric layer; and a second dielectric layer covering the first dielectric layer and the phase-change storage cap wherein the second dielectric layer defines an air gap in the recess.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: September 27, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Li-Shu Tu