Abstract: A method by which silicon nanostructures may be selectively coated with molecules or biomolecules using an electrochemical process. This chemical process may be employed as a method for coating many different nanostructures within a circuit, each with a different molecular or biomolecular material. The density of devices within a circuit of devices that can be coated with different molecules is limited only by the ability to electronically address each device separately. This invention has applications toward the fabrication of molecular electronic circuitry and toward the fabrication of nanoelectronic molecular sensor arrays.
Type:
Grant
Filed:
June 23, 2004
Date of Patent:
August 26, 2008
Assignee:
California Institute of Technology
Inventors:
James R. Heath, Yuri Bunimovich, Guanglu Ge, Kristen Beverly, John Nagarah, Michael Roukes, Peter Willis
Abstract: A functional molecular element whose functions can be controlled by an electric field based on a new principle. A Lewis base molecule (14) with positive permittivity anisotropy or a dipole moment in the major axis direction of the molecule is disposed, via a metal ion (3) that can act as a Lewis acid, in a pendant-like form on a key molecule (2) in the form of a line or film that has a conjugated system and exhibits conductivity, thereby forming a functional molecular element 1 that can realize a function where the conformation changes due to the application of an electric field. The conductive key molecule (2) and the Lewis base molecule (14) form a complex with the metal ion (3). When an electric field is applied in a direction perpendicular to the plane of the paper in FIG. 1(b), for example, the Lewis base molecule (14) performs a 90° “neck twisting” movement with the up-down direction in the drawing as the axis.
Type:
Grant
Filed:
December 25, 2003
Date of Patent:
August 5, 2008
Assignee:
Sony Corporation
Inventors:
Eriko Matsui, Oliver Harnack, Nobuyuki Matsuzawa, Akio Yasuda
Abstract: These heterodiamondoids are diamondoids that include heteroatoms in the diamond lattice structure. The heteroatoms may be either electron donating, such that an n-type heterodiamondoid is created, or electron withdrawing, such that a p-type heterodiamondoid is made. Bulk materials may be fabricated from these heterodiamondoids, and the techniques involved include chemical vapor deposition, polymerization, and crystal aggregation. Junctions may be made from the p-type and n-type heterodiamondoid based materials, and microelectronic devices may be made that utilize these junctions. The devices include diodes, bipolar junction transistors, and field effect transistors.
Type:
Grant
Filed:
July 16, 2003
Date of Patent:
July 22, 2008
Assignee:
Chevron U.S.A. Inc.
Inventors:
Shenggao Liu, Jeremy E. Dahl, Robert M. Carlson
Abstract: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.
Type:
Grant
Filed:
August 3, 2005
Date of Patent:
June 24, 2008
Assignee:
International Business Machines Corporation
Abstract: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel.
Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
Abstract: This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a method is provided that involves contacting a surface/electrode with a compound of formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.
Type:
Grant
Filed:
April 30, 2004
Date of Patent:
December 25, 2007
Assignee:
The North Carolina State University
Inventors:
David F. Bocian, Werner G. Kuhr, Jonathan S. Lindsey, Veena Misra
Abstract: A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite with a soft magnetic layer comprised of discontinuous particles less than 2 nm in size on the seed layer and a capping layer of Ru, Ta, or Cu on the soft magnetic layer. Fringing fields and hysteresis effects from continuous ferromagnetic cladding layers associated with switching the magnetic state of an adjacent MTJ are totally eliminated because of the super-paramagnetic character of the soft magnetic layer at room temperature. The soft magnetic layer has near zero magnetostriction, very high susceptibility, and may be made of Ni˜80Fe˜20, Ni˜30Fe˜70, Co˜90Fe˜10, or CoNiFe.
Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
Type:
Grant
Filed:
January 30, 2006
Date of Patent:
November 20, 2007
Assignee:
Samsung Electronics, Co., Ltd.
Inventors:
Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.
Abstract: A semiconductor device, which is arranged in a semiconductor body (1), and which comprises at least one source region (4) and at least one drain region (5), each being of the first conductivity type, and at least one body (8) of the second conductivity type, arranged between source region (4) and drain region (5), and at least one gate electrode (10) which is isolated with respect to the semiconductor body (1) via an isolation layer (9). Said isolation layer (9) comprises polarizable particles, which are composed of a nanoparticulate isolating core and a sheath of polarizable anions or polarizable cations. The isolation layer (9) exhibits a high dielectric constant ?.
Type:
Grant
Filed:
March 8, 2004
Date of Patent:
February 6, 2007
Assignee:
NXP B.V.
Inventors:
Cornelis Reinder Ronda, Stefan Peter Grabowski