Abstract: A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.

Abstract: A magnetic film stack is composed of a synthetic antiferromagnet including a plurality of ferromagnetic layers, adjacent two of which are antiferromagnetically coupled through a non-magnetic layer; and a reversal inducing layer exhibiting ferromagnetism. The reversal inducing layer is ferromagnetically coupled to the synthetic antiferromagnet, and designed to have a coercive field smaller than a magnetic field at which antiferromagnetic coupling within the synthetic antiferromagnet starts to be decoupled.

Abstract: Magnetic or magnetoresistive random access memories (MRAMs) are implemented in a variety of arrangements and methods. Using one such arrangement, a matrix is implemented with magnetoresistive memory cells logically organized in rows and columns, each memory cell including a magnetoresistive element. The matrix has a set of column lines, a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column, wherein each column line has a forward column line and a return column line arranged on opposite sides of the magnetoresistive element and offset from one another for forming a return path for current in that column line.

Abstract: A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so that variations in a resistance value of a resistor are suppressed. Also, the gate electrodes of the MIS transistors and the like are exposed when thermal treatment for activating an impurity, and therefore breakdown of respective gate insulation films of the MIS transistors hardly occurs.

Abstract: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.

Abstract: A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron nanostructures are grown on a metal-substituted MCM-41 template with pores having a uniform pore diameter of less than approximately 4 nm, and can be doped with a Group Ia or Group IIa electron donor element during or after growth of the nanostructure. Preliminary data based on magnetic susceptibility measurements suggest that Mg-doped boron nanotubes have a superconducting transition temperature on the order of 100 K.

Abstract: EEPROMS Using Carbon Nanotubes for Cell Storage. An electrically erasable programmable read only memory (EEPROM) cell includes cell selection circuitry and a storage cell for storing the informational state of the cell. The storage cell is an electro-mechanical data retention cell in which the physical positional state of a storage cell element represents the informational state of the cell. The storage cell element is a carbon nanotube switching element. The storage is writable with supply voltages used by said cell selection circuitry. The storage is writable and readable via said selection circuitry with write times and read times being within an order of magnitude. The write times and read times are substantially the same. The storage has no charge storage or no charge trapping.

Abstract: New kinds of nano-scale computational architectures using spin waves as a physical mechanism for device interconnection are described. A method for operating a logic device having a spin wave bus includes the step of receiving an input signal representing information. A spin wave is excited with the information coded in an aspect of the spin wave in response to receiving the input signal. The spin wave is propagated through a spin wave bus having an associated polarization. The information associated with the spin wave is determined in response to propagating the spin wave through the spin wave bus.

Abstract: Means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.

Abstract: A mesh source wiring composed of first source wirings, second source wirings, and contacts for mesh source wiring is connected, through contacts for strap source wiring, with strap source wirings formed on a wiring layer nearer a substrate than wiring layers where the mesh source wiring is formed. The cell source wirings formed on a wiring layer nearer the substrate than the wiring layer where the strap source wirings are formed are connected with the strap source wirings through contacts for cell source wiring.

Abstract: A ballistic memory cell structure employing ballistic transistor technology for switching between a read state and a store state is disclosed. The memory cell structure includes substrate structures forming a side wall and a main chamber for defining a linear ballistic channel between the two. The main chamber is formed to include a deflection channel with deflective surfaces to deflect an electron emitted from an electron source into the memory cell structure. Deflection controllers are coupled to the substrate structures for generating biasing fields that adjust the trajectory of electrons flowing through the linear ballistic channel and the deflection channel. Logic output terminals are positioned beyond channel exits for registering exiting electrons and determining a read or store state.

Abstract: Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate.

Abstract: A metal oxide nanostructure is formed by oxidizing metallic metal in the presence of a solution containing a liquid ligand to form a metal-ligand complex, and decomposing the metal-ligand complex to form the metal oxide nanostructure. The metal-ligand complex can be a complex of zinc or copper with formamide. In one form, the nanostructure forms ZnO nanorods having a diameter of 10 to 1000 nm, where the nanorods having a hexagonal crystallographic morphology, and the nanorods are oriented perpendicular to a substrate.

Abstract: A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape.

Abstract: An improved microelectromechanical switch assembly comprises a linearly movable switch rod constrained via a switch bearing, the switch rod being actuated by electrostatic deflection. Movement of the switch rod to one end of its travel puts the switch assembly in a closed state while movement of the switch rod to the other end of its travel puts the switch assembly in an open state. In an embodiment of the invention, one or both of the switch rod and the switch bearing are fabricated of a carbon nanotube. The improved microelectromechanical switch assembly provides low insertion loss and long lifetime in an embodiment of the invention.

Abstract: An information storage device includes a substrate and a shape memory alloy film established on the substrate. The shape memory alloy film may receive, supply, and store digital information. One or more thermoelectric modules is/are nanoimprinted between the substrate and the shape memory alloy film. The thermoelectric modules(s) is adapted to selectively erase at least some of the digital information from the shape memory alloy film.

Abstract: The present invention concerns a method for modyfing at least an electronic property of a carbon nanotube or nanowire comprising exposing said nanotube or nanowire to an acid having the formula (I) wherein R1, R2 and R3 are chosen in the group comprising (H, F, Cl, Br, I) with at least one of R1, R2 and R3 being different from H. At least part of the nanotube or nanowire may be a channel region of a field effect transistor.

Abstract: A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

Abstract: Highly planar non-polar GaN films are grown by hydride vapor phase epitaxy (HVPE). The resulting films are suitable for subsequent device regrowth by a variety of growth techniques.