Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region.

Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.

Abstract: Device layouts for integrated circuit devices that include threshold voltage shift induced by placement of alternate work function metals adjacent active gates are disclosed. The device layouts include a single epitaxy for active regions in the device with common source/drain regions among the active region rows in the layouts. Metal gate sections above one or more rows of active regions may be replaced with metal of a different work function in inactive regions of the layout. The different work function metal in the inactive regions will induce threshold voltage shift in adjacent (neighboring) active transistors of the device layouts.

Abstract: Systems and methods for manufacturing semiconductor devices. The system can include a semiconductor device. The semiconductor device can include a semiconductor shell that extends along a vertical direction. The semiconductor device can include a first metal structure surrounded by a lower portion of the semiconductor shell. The semiconductor device can include a dielectric structure above the first metal structure. The semiconductor device can include a second metal structure through the dielectric structure.

Abstract: Aspects of the present disclosure provide 3D semiconductor structures and methods for fabricating the same. For example, the method can include forming a first multilayer stack over a substrate, forming a second multilayer stack over the first multilayer stack, forming a first opening through the first and second multilayer stack until uncovering a top surface of the substrate, forming in the first opening a first vertical field-effect transistor (VFET) over the substrate, and forming in the first opening a second VFET over the first VFET. The first VFET can include a first channel having a first length corresponding to a first thickness of a first layer of the first multilayer stack. The second VFET can include a second channel having a second length corresponding to a second thickness of a second layer of the second multilayer stack. The second thickness can be different from the first thickness.

Abstract: A display panel and a display device are provided. The display panel includes a substrate; a light-shielding metal layer disposed on a side of the substrate, wherein the light-shielding metal layer includes a first trace disposed in a frame area; a driving circuit layer disposed on a side of the light-shielding metal layer away from the substrate, wherein the driving circuit layer includes a pixel driving circuit disposed in the display area and a gate driving circuit disposed in the frame area; a first electrode disposed on a side of the driving circuit layer away from the substrate; a light-emitting layer disposed on a side of the first electrode away from the substrate; and a second electrode disposed on a side of the light-emitting layer away from the substrate, wherein the first trace and the gate driving circuit are at least partially overlapped.

Abstract: Provided are method for managing chip manufacturing equipment, apparatus, electronic device and storage medium. The method incudes: determining, for each furnace tube device in target area, processing precision of the furnace tube device, through a heating uniformity result of the furnace tube device, processing test result of test piece, and factory parameters and marking a processing precision label; determining, when it is detected that a first rule is set in first furnace tube device, a second furnace tube device having device capability same as the first furnace tube device, and determining a target second furnace tube device having processing precision label same as that required by the first rule; determining priority synchronization sequence of the target second furnace tube device according to the processing precision of the target second furnace tube device; and synchronizing the first rule to the target second furnace tube device according to the priority synchronization sequence.

Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.

Abstract: A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a first transistor, located on the substrate; a second transistor, located above the first transistor; and a gate structure, the gate structure including a first gate layer and a second gate layer, which connected to each other, the first gate layer surrounding the first transistor and the second gate layer surrounding the second transistor; an extension direction of the first transistor and an extension direction of the second transistor are both perpendicular to the substrate.

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.

Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.

Abstract: An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.

Abstract: A semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a bottom source/drain (S/D) region directly contacting a bottom surface of the first and second set of fins, and a top S/D region directly contacting a top surface of the first and second set of fins. A high-k metal gate (HKMG) is disposed between fins of the first set of fins and between fins of the second set of fins. The HKMG directly contacts sidewalls of the dielectric pillar. A width of the HKMG between the first set of fins is equal to a width of the HKMG between the second set of fins.

Abstract: A display panel including a light emitting panel; and a color conversion panel with a surface opposite a surface of the light emitting panel. The light emitting panel is configured to emit incident light including a first light and a second light. The color conversion panel includes a color conversion layer including two or more color conversion regions, a color conversion region includes a first region corresponding to the green pixel, the first region includes a matrix and a first composite dispersed within the matrix and including a plurality of luminescent nanostructures, and the spectral overlap between a UV-Vis absorption spectrum of the luminescent nanostructures, the maximum emission peak of the first light, and the maximum emission peak of the second light satisfies the following equation: B/A?about 0.6 A and B are as defined.

Abstract: A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: A display device includes: a light-emitting element at a display area; a driving element electrically connected to the light-emitting element; an encapsulation layer covering the light-emitting element; a touch sensor on the encapsulation layer; a connection pad at a bonding area, the connection pad including a lower conductive layer, an intermediate conductive layer on the lower conductive layer, and an upper conductive layer on the intermediate conductive layer; a cladding layer covering at least a side surface of the intermediate conductive layer and including an organic material; a passivation layer covering an upper surface of the cladding layer and including an inorganic material, a portion of the passivation layer being located under the upper conductive layer; and a driving circuit attached to the connection pad.

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.