Patents Examined by Michael M Trinh
  • Patent number: 12278285
    Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: April 15, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungchan Yun, Donghwan Han
  • Patent number: 12274098
    Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: April 8, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungho Lee, Hyuk An, Hyuk Soon Choi
  • Patent number: 12266657
    Abstract: An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Xuan Huang, Shih-Wei Peng, Te-Hsin Chiu, Hou-Yu Chen, Kuan-Lun Cheng, Jiann-Tyng Tzeng
  • Patent number: 12255204
    Abstract: A semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a bottom source/drain (S/D) region directly contacting a bottom surface of the first and second set of fins, and a top S/D region directly contacting a top surface of the first and second set of fins. A high-k metal gate (HKMG) is disposed between fins of the first set of fins and between fins of the second set of fins. The HKMG directly contacts sidewalls of the dielectric pillar. A width of the HKMG between the first set of fins is equal to a width of the HKMG between the second set of fins.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: March 18, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker
  • Patent number: 12256621
    Abstract: A display panel including a light emitting panel; and a color conversion panel with a surface opposite a surface of the light emitting panel. The light emitting panel is configured to emit incident light including a first light and a second light. The color conversion panel includes a color conversion layer including two or more color conversion regions, a color conversion region includes a first region corresponding to the green pixel, the first region includes a matrix and a first composite dispersed within the matrix and including a plurality of luminescent nanostructures, and the spectral overlap between a UV-Vis absorption spectrum of the luminescent nanostructures, the maximum emission peak of the first light, and the maximum emission peak of the second light satisfies the following equation: B/A?about 0.6 A and B are as defined.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: March 18, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Gon Kim, Shin Ae Jun, Deukseok Chung, Nayoun Won, Sung Hun Lee, Byoung Ki Choi
  • Patent number: 12237330
    Abstract: A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 25, 2025
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Jean-Pierre Colinge, Bernard Previtali
  • Patent number: 12224203
    Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: February 11, 2025
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Kangguo Cheng, Thomas J. Haigh, Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen, Chanro Park, Tenko Yamashita
  • Patent number: 12219856
    Abstract: A display device includes: a light-emitting element at a display area; a driving element electrically connected to the light-emitting element; an encapsulation layer covering the light-emitting element; a touch sensor on the encapsulation layer; a connection pad at a bonding area, the connection pad including a lower conductive layer, an intermediate conductive layer on the lower conductive layer, and an upper conductive layer on the intermediate conductive layer; a cladding layer covering at least a side surface of the intermediate conductive layer and including an organic material; a passivation layer covering an upper surface of the cladding layer and including an inorganic material, a portion of the passivation layer being located under the upper conductive layer; and a driving circuit attached to the connection pad.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Yup Kim, Deukjong Kim, Hagyeong Song
  • Patent number: 12211794
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 28, 2025
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Anil Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Patent number: 12205850
    Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Patent number: 12191217
    Abstract: The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 7, 2025
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongqian Li, Can Yuan, Meng Li, Xuehuan Feng, Zhongyuan Wu, Zhidong Yuan
  • Patent number: 12191210
    Abstract: Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 7, 2025
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner, Partha Mukhopadhyay
  • Patent number: 12148658
    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: November 19, 2024
    Assignee: InnoLux Corporation
    Inventors: Cheng-Chi Wang, Yeong-E Chen, Cheng-En Cheng
  • Patent number: 12148733
    Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Hsien-Ju Tsou
  • Patent number: 12142664
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Patent number: 12144234
    Abstract: A display device comprises a substrate including display and peripheral areas, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The semiconductor element is disposed in the display area on the substrate, and the pixel structure is disposed on the semiconductor element. The dummy patterns which have stacked structure are disposed in the peripheral area on the substrate, and contain a material identical to a material constituting the semiconductor element. The dummy patterns are arranged in a grid shape in different layers, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of dummy patterns which are adjacent to each other in the different layers among the dummy patterns are overlapped each other in a direction from the substrate to the pixel structure.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: November 12, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sewan Son, Moo Soon Ko, Ji Ryun Park, Jin Sung An, Min Woo Woo, Seong Jun Lee, Wang Woo Lee, Jeong-Soo Lee, Ji Seon Lee, Deuk Myung Ji
  • Patent number: 12131957
    Abstract: Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence. Scanning probe microscopy may be used to provide conductance data. Conductance data may relate to device characteristics that are normally not available until the conclusion of device manufacturing. The substrates may be selectively treated to ameliorate a condition revealed by the data. Some substrates may be selectively discarded based on the data to avoid the expense of further processing. A process maintenance operation may be selectively carried out based on the data.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang
  • Patent number: 12132047
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing a semiconductor device. Every two first wires of a first conductive layer of the semiconductor device have a common end, and every two second wires of a second conductive layer of the semiconductor device have a common end.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 29, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kui Zhang
  • Patent number: 12132105
    Abstract: There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 29, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hojun Choi, Ji Seong Kim, Min Cheol Oh, Ki-Il Kim
  • Patent number: 12125752
    Abstract: A method for grinding the wafer includes: an initial wafer of which an edge has a test address is provided; a recombined water of which the test address is located in the middle is formed; a following circulation step is performed: a protective layer at least located above the test address is formed on an existing layer of the recombined water; the uncovered existing layer is grinded; the protective layer and the existing layer which is remaining are removed. It is determined whether the test address is exposed, if not, the next circulation step is performed.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: October 22, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jiabao Chen