Abstract: A display device includes a first display substrate and a second display substrate. The first display substrate includes a first base, a first electrode disposed on the first base, a second electrode spaced apart from the first electrode, and a light emitting element disposed between the first electrode and the second electrode. The second display substrate faces the first display substrate and is configured to receive light emitted from the light emitting element. The second display substrate includes a second base, a first color filter disposed on a surface of the second base, and a first wavelength conversion pattern disposed on the first color filter. The first wavelength conversion pattern includes a first surface facing the first display substrate, and a second surface facing the first surface and the first color filter. The first surface includes a curved surface portion recessed toward the second surface.

Abstract: A laser marking device includes a laser emission unit configured to emit a laser beam to a first surface of an object to be processed, and a pressing unit configured to press a second surface that is opposite to the first surface of the object to be processed to make the first surface of the object to be flat. The pressing unit includes a first pressing portion configured to press an edge area of the second surface in a contact manner, and at least one second pressing portion configured to press a middle area of the second surface in a non-contact manner to maintain a separation distance from the second surface within a certain distance.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region.

Abstract: A device includes a semiconductor substrate having a first region and a second region. The device further includes a first pair of fin structures within the first region. The device further includes a second pair of fin structures within the second region. A top surface of the semiconductor surface between fin structures within the first pair is higher than a top surface of the semiconductor surface between the first pair and the second pair.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include forming a multilayer stack on a substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming at least one opening through the multilayer stack to uncover the substrate and forming at least two vertical channel structures within the opening that are stacked on each other. The vertical channel structures can have source, gate and drain regions being in contact with the metal layers of the multilayer stack, respectively. The method can also include removing a central portion of the vertical channel structures and filling the central portion of the vertical channel structures with a dielectric core. The dielectric core can isolate the vertical channel structures from each other and from the substrate.

Abstract: A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench.

Abstract: A method and apparatus are provided. In an example, a volume portion of the solid body is exposed to light waves of different wavelengths, wherein the light waves are partly reflected at surfaces of the solid body. Light parameters of the reflected light waves are at least partly acquired using a sensor device. Distance information and/or intensity information are/is ascertained from at least a portion of the acquired light parameters. A thickness and/or a transmittance of the solid body in the volume portion are/is determined based upon the distance information and/or the intensity information. Laser radiation is introduced into the volume portion to produce a modification in the interior of the solid body, wherein at least one laser parameter of the laser radiation is set at least depending on the thickness and/or the transmittance such that the modification is at a predefined distance from a surface of the solid body.

Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; providing a supporting platform having a plurality of vacuum valves; disposing a substrate on the supporting platform; applying vacuum attraction to a portion of the substrate through a portion of the plurality of vacuum valves, wherein the portion of the substrate corresponding to the vacuum attraction is defined as an attracted region; and performing an exposure on a portion of the attracted region, wherein an area of the attracted region is larger than the basic working area and smaller than an area of the supporting platform.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other.

Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: A quantum dot comprising zinc, tellurium, and selenium and not comprising cadmium, wherein a maximum luminescent peak of the quantum dot is present in a wavelength range of greater than about 470 nanometers (nm) and a quantum efficiency of the quantum dot is greater than or equal to about 10%, and wherein the quantum dot comprises a core comprising a first semiconductor nanocrystal and a semiconductor nanocrystal shell disposed on the core.

Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.

Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit torque wiring layer which extends in an X direction; and a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer, wherein the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and wherein the easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends.

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Abstract: A quantum dot comprising zinc, tellurium, and selenium and not comprising cadmium, wherein a maximum luminescent peak of the quantum dot is present in a wavelength range of greater than about 470 nanometers (nm) and a quantum efficiency of the quantum dot is greater than or equal to about 10%, and wherein the quantum dot comprises a core comprising a first semiconductor nanocrystal and a semiconductor nanocrystal shell disposed on the core.