Abstract: A display device comprises a substrate including display and peripheral areas, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The semiconductor element is disposed in the display area on the substrate, and the pixel structure is disposed on the semiconductor element. The dummy patterns which have stacked structure are disposed in the peripheral area on the substrate, and contain a material identical to a material constituting the semiconductor element. The dummy patterns are arranged in a grid shape in different layers, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of dummy patterns which are adjacent to each other in the different layers among the dummy patterns are overlapped each other in a direction from the substrate to the pixel structure.

Abstract: A vertical transport field-effect transistor array includes continuous spacers at cell edges that are formed following a replacement metal gate process. Techniques for fabricating the transistor array include forming trenches extending along the fin edges of the array to provide access to sacrificial gates, replacing the sacrificial gates with gate stacks, and forming the continuous spacers to encapsulate the gate stacks once formed. Removal of interlevel dielectric material from the array is not required for gate replacement. Bottom source/drain contacts may be formed in the trenches and in adjoining relation to the continuous spacers.

Abstract: A method for manufacturing a vertical transistor device includes forming a plurality of fins on a substrate, and forming a gate dielectric layer on the fins and on the substrate adjacent the fins. In the method, one or more sacrificial layers are formed on the gate dielectric layer, and portions of the gate dielectric layer and the one or more sacrificial layers are removed to define a plurality of gate regions. The method also includes depositing a dielectric fill layer in gaps left by the removed gate dielectric and sacrificial layers, and selectively removing the remaining portions of the one or more sacrificial layers to form a plurality of vacant areas in the gate regions. First and second gate structures are respectively formed in first and second vacant areas of the plurality of vacant areas. The first and second gate structures are recessed to a uniform height.

Abstract: The present application provides an organic light-emitting diode display. The display includes a plurality of pixel defining units, the pixel defining unit includes a first portion formed on a switch array layer which is not covered by anode electrodes and a second portion formed on the anode electrode, a groove is defined at the first portion, and at least one opening is defined at the second portion; an organic light-emitting layer including a plurality of organic light-emitting units, the organic light-emitting layer is formed on the anode electrodes which are not covered by the second portion.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

Abstract: A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

Abstract: A display apparatus includes a display area and a non-display area, a sub-pixel in the display area, and a pixel-defining layer which defines an area of the sub-pixel. The sub-pixel includes an adjacent sub-pixel arranged in the display area to be adjacent to the non-display area, and an internal sub-pixel arranged in the display area, and the adjacent sub-pixel and the internal sub-pixel implement the same color and have different shapes in a plan view.

Abstract: A display apparatus includes: a substrate including a thin-film transistor including an electrode, a non-display area, and a pad area including a lower and an upper conductive layer facing each other with an insulating layer therebetween. The lower conductive layer includes: a first conductive layer defining an end surface of the display apparatus, and a second conductive layer spaced apart from the first conductive layer to define a space between the first and second conductive layers, the insulating layer defines a first opening portion corresponding to the space, and the upper conductive layer is in a same layer as the electrode of the thin-film transistor, the upper conductive layer extending into the first opening portion corresponding to the space between the first and second conductive layers.

Abstract: A chip is described including a semiconductor layer including doped regions; a metallization layer on the semiconductor layer and at least one cell row including p-channel field effect transistors and n-channel field effect transistors, wherein the doped regions form source regions and drain regions of the p-channel field effect transistors and the n-channel field effect transistors; contacts extending from the source regions, the drain regions and gate regions of the p-channel field effect transistors and the n-channel field effect transistors to the metallization layer, wherein the metallization layer is structured in accordance with a metallization grid such that the p-channel field effect transistors and the n-channel field effect transistors are connected to form one or more logic gates.

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

Abstract: Provided is a method of measuring the concentration of Fe in a p-type silicon wafer by an SPV method enabling improvement in the measurement accuracy for Fe concentrations of 1×109/cm3 or less. The method of measuring the concentration of Fe in a p-type silicon wafer includes measuring an Fe concentration in the p-type silicon wafer based on measurement using an SPV method. The measurement is performed in an atmosphere in which the total concentration of Na+, NH4+, and K+ is 1.750 ?g/m3 or less, and the total concentration of F?, Cl?, NO2?, PO43?, Br?, NO3?, and SO42? is 0.552 ?g/m3 or less.

Abstract: Provided is a light-emitting device that can display an image with a wide color gamut or a novel light-emitting element. The light-emitting device includes a plurality of light-emitting elements each of which includes an EL layer between a pair of electrodes. Light obtained from a first light-emitting element through a first color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than 0.680 and less than or equal to 0.720 and a chromaticity y of greater than or equal to 0.260 and less than or equal to 0.320. Light obtained from a second light-emitting element through a second color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than or equal to 0.130 and less than or equal to 0.250 and a chromaticity y of greater than 0.710 and less than or equal to 0.810. Light obtained from a third light-emitting element through a third color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than or equal to 0.120 and less than or equal to 0.

Abstract: An electronic component mounting device (100) bonds a semiconductor die (150) to a substrate by thermocompression bonding, and seals, using an insulating resin, a gap between the semiconductor die (150) and the substrate. The electronic component mounting device is provided with: a film cutting mechanism (200) for cutting a long film (210) into cut pieces; and a mounting tool (110), which vacuum-sucks the semiconductor die (150), and bonds the die to the substrate by thermocompression bonding. Consequently, in the electronic component mounting device (100) that moves a mounting head in the horizontal direction, adhesion of the insulating resin to the mounting tool can be suppressed.

Abstract: Reliable resin packages and semiconductor light-emitting devices using the resin package can include a printed circuit board including a resin layer, metallic layers formed on a top surface of the resin layer and underneath a bottom surface of the resin layer and a frame arranged from a top surface of the printed circuit board toward a bottom surface of the printed circuit board. The semiconductor light-emitting device using the resin package can prevent the printed circuit board from warping toward the frame when forming the frame incorporating the printed circuit board because a total of each thickness of the metallic layers formed on the top surface and underneath the bottom surface of the resin layer can be thicker than a thickness of the resin layer. Thus, the present invention can provide the semiconductor light-emitting devices having high reliability, which can be used as a light source for vehicle lamps, etc.

Abstract: A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.

Abstract: Exemplary methods of producing a semiconductor substrate may include characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias. The methods may include determining a fill rate for each via within the zonal distribution of the plurality of vias. The methods may include modifying a die pattern to adjust via fill rates between two zones of vias. The methods may also include producing a substrate according to the die pattern.

Abstract: A semiconductor assembly manufacturing method includes: providing a substrate including a first conductive circuit; disposing a first electronic component on a side of the substrate; forming a first plastic seal layer covering the substrate and the first electronic component; setting up a plurality of grooves in the first plastic seal layer, the groove exposes at least a portion of the first conductive circuit of the substrate; and filling a conductive material in each of the grooves by vacuum printing so as to form a second conductive circuit electrically connected to the first conductive circuit of the substrate, and a second electronic component pad position thereof in the first plastic seal layer.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, an emitter region, and a collector region. The epitaxial layer is disposed over the substrate and has a first conductivity type. The drift region is disposed in the epitaxial layer and has a second conductivity type that is the opposite of the first conductivity type. The emitter region is disposed in the epitaxial layer outside the drift region. The collector region is disposed in the drift region. The semiconductor device also includes a doped region. The doped region is disposed adjacent to the bottom surface of the drift region and has the first conductivity type.