Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: An arrangement apparatus includes a stage, an arrangement part, and a control part. The stage supports a substrate. The arrangement part holds a die and arranges multiple dies on the substrate supported by the stage. The control part has a map data indicating arrangement positions of the dies and generated based on a positional relationship among patterns formed by an exposure apparatus, and controls, based on the map data, relative positions between the stage and the arrangement part when arranging the dies on the substrate.

Abstract: Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.

Abstract: A method for semiconductor metrology includes depositing first and second overlying film layers on a semiconductor substrate and patterning the layers to define an overlay target. The target includes a first grating pattern in the first layer, including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction, and a second grating pattern in the second layer, including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating. The second grating pattern has a nominal offset relative to the first grating pattern by first and second displacements in the first and second directions, respectively. A scatterometric image of the substrate is captured and processed to estimate an overlay error between the patterning of the first and second layers.

Abstract: A method and apparatus are provided. In an example, a volume portion of the solid body is exposed to light waves of different wavelengths, wherein the light waves are partly reflected at surfaces of the solid body. Light parameters of the reflected light waves are at least partly acquired using a sensor device. Distance information and/or intensity information are/is ascertained from at least a portion of the acquired light parameters. A thickness and/or a transmittance of the solid body in the volume portion are/is determined based upon the distance information and/or the intensity information. Laser radiation is introduced into the volume portion to produce a modification in the interior of the solid body, wherein at least one laser parameter of the laser radiation is set at least depending on the thickness and/or the transmittance such that the modification is at a predefined distance from a surface of the solid body.

Abstract: A method of measuring the concentration of Fe in a p-type silicon wafer by an SPV method enabling improvement in the measurement accuracy for Fe concentrations of 1×109/cm3 or less. The method of measuring the concentration of Fe in a p-type silicon wafer includes measuring an Fe concentration in the p-type silicon wafer based on measurement using an SPV method. The measurement is performed in an atmosphere in which the total concentration of Na+, NH4+, and K+ is 1.750 ?g/m3 or less, and the total concentration of F?, Cl?, NO2?, PO43?, Br?, NO3?, and SO42? is 0.552 ?g/m3 or less.

Abstract: A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

Abstract: A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines.

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: In a method, a structure including two or more materials having different coefficients of thermal expansion is prepared, and the structure is subjected to a cryogenic treatment. In one or more of the foregoing and following embodiments, the structure includes a semiconductor wafer and one or more layers are formed on the semiconductor wafer.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: A method of polishing a substrate includes polishing a conductive layer on the substrate at a polishing station, monitoring the layer with an in-situ eddy current monitoring system to generate a plurality of measured signals values for a plurality of different locations on the layer, generating thickness measurements the locations, and detecting a polishing endpoint or modifying a polishing parameter based on the thickness measurements. The conductive layer is formed of a first material having a first conductivity. Generating includes calculating initial thickness values based on the plurality of measured signals values and processing the initial thickness values through a neural network that was trained using training data acquired by measuring calibration substrates having a conductive layer formed of a second material having a second conductivity that is lower than the first conductivity to generated adjusted thickness values.

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

Abstract: A semiconductor device with a fuse component is provided. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The gate metal layer is configured to receive a voltage to change a resistivity between the gate metal layer and the active region.

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

Abstract: A quantum dot comprising zinc, tellurium, and selenium and not comprising cadmium, wherein a maximum luminescent peak of the quantum dot is present in a wavelength range of greater than about 470 nanometers (nm) and a quantum efficiency of the quantum dot is greater than or equal to about 10%, and wherein the quantum dot comprises a core comprising a first semiconductor nanocrystal and a semiconductor nanocrystal shell disposed on the core.

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.