Abstract: A susceptor for holding a semiconductor wafer with an orientation notch during deposition of a layer on the wafer comprises a susceptor ring having a placement area for placing the semiconductor wafer in the edge region of a back side of the semiconductor wafer and a step-shaped outer delimitation of the susceptor ring adjoining the placement area. The susceptor has four positions at which the structure differs from the structure at four further positions, the spacing from one of the four positions to the next of the four positions being 90°, the spacing from one of the four positions to the next further position being 45°, one of the four positions being a notch position at which the structure of the susceptor differs from the structure of the susceptor at the three other positions of the four positions of the susceptor.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: The present disclosure provides an organic transistor and a manufacturing method thereof, an array substrate, and a display device. The method for manufacturing the organic transistor includes: applying a photoresist on a side of an organic insulating layer; patterning the photoresist to form a confinement well; adding a solution of an organic semiconductor material and an orthogonal solvent to the confinement well; volatilizing the orthogonal solvent by an annealing process to induce directional growth of single crystal of the organic semiconductor material in the confinement well, thereby obtaining an organic single crystal layer; and removing remaining photoresist and using the organic single crystal layer as an active layer. The embodiment of the present disclosure produces an organic single crystal in a flexible display device at a low temperature, and the organic single crystal can be used as an active layer, resulting in an organic transistor having high mobility and stability.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for fabricating the MOSFET are disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

Abstract: In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.

Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit torque wiring layer which extends in an X direction; and a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer, wherein the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and wherein the easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends.

Abstract: A method for fabricating MOSFET is disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.

Abstract: Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.

Abstract: A method for fabricating a semiconductor device includes stacking a first mold layer and a first supporter layer, forming a first supporter pattern by etching the first supporter layer to expose the first mold layer, forming an insulating layer to cover the exposed first mold layer and the first supporter pattern, stacking a second mold layer and a second supporter layer on the insulating layer, forming a contact hole by dry-etching the second supporter layer, the second mold layer, the insulating layer, the first supporter pattern, and the first mold layer, forming a lower electrode within the contact hole, removing the first mold layer, the second mold layer, and the insulating layer, and forming an upper electrode on the lower electrode and the first supporter pattern, wherein, during the dry-etching, dry etching rates of the first supporter pattern and the insulating layer are the same.

Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract: Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip package structure further includes a first photosensitive layer formed around sidewalls of the first chip and covering a top surface of the first chip and a second chip disposed over the first photosensitive layer. In addition, the first chip and the second chip are separated by the first photosensitive layer.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: An etch stop layer is formed on a lower wiring. An interlayer insulating film covers the lower wiring and the etch stop layer. A via exposes an upper surface of the etch stop layer, in the interlayer insulating film. A first filler is formed in the via. The first filler is etched to a first filler pattern. A second filler is formed on the first filler pattern and is etched to a second filler pattern. A trench is formed by etching the interlayer insulating film. The first and second filler patterns are etched during the forming of the trench to form a residual filler pattern. The residual filler pattern and the etch stop layer are removed and a wiring structure is formed electrically connected to the lower wiring. The via includes lower and upper portions and the trench includes the upper portion of the via.

Abstract: A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.